Virtualizing precise event based sampling

Patent metadata

Field	Value
Publication number	US-10496522-B2
Application number	US-201815972390-A
Country	US
Kind code	B2
Filing date	May 7, 2018
Priority date	Jun 28, 2016
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

First claim

What is claimed is:

1. A processor comprising:
a core to execute and retire a plurality of instructions for a virtual machine, the core operatively coupled to memory;
a reload register coupled to the core and to store a plurality of reload values for different virtual machines, the plurality of reload values comprising a reload value for the virtual machine;
a performance monitoring counter (PMC) register coupled to the reload register;
an event-based sampler operatively coupled to the reload register and the PMC register, wherein the event-based sampler includes first circuitry to:
load the reload value of the virtual machine into the PMC register;
increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the plurality of instructions; and
upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value:
execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution; and
reload the reload value from the reload register into the PMC register.

2. The processor of claim 1 , further comprising a processor tracer including second circuitry to capture trace data produced by execution of the plurality of instructions and to format the trace data as a plurality of trace data packets.

3. The processor of claim 2 , further comprising a memory buffer for use by the virtual machine, and the second circuitry is further to:
format the field data into a group of record packets corresponding to the elements;
interleave the group of record packets between ones of the plurality of trace data packets of the trace data, to generate a combined packet stream; and
store the combined packet stream in the memory buffer as a series of output pages.

4. The processor of claim 3 , wherein the core is further to generate a page fault when accessing a guest physical address for an output page of the series of output pages that is not mapped to a host physical address of the memory, and wherein a virtual machine monitor (VMM) is further to pause the virtual machine to handle the page fault.

5. The processor of claim 3 , wherein the core is further to execute a virtual machine monitor (VMM), and wherein to store the combined packet stream in the memory buffer as the series of output pages, the second circuitry is to:
while filling a first output page, prefetch a second output page;
test whether the second output page is mapped to a host physical page of the memory; and
trigger a virtual machine exit to request the VMM to map the second output page to the memory responsive to detecting that the second output page is not mapped to the memory.

6. The processor of claim 2 , wherein the event-based sampler is further to execute the microcode to perform a series of signal operations that transmit the field data for the elements of the sampling record in a predetermined order to the processor tracer.

7. The processor of claim 1 , further comprising a virtual machine control structure (VMCS) register, that when enabled, is to cause the event-based sampler to remain enabled upon exiting the virtual machine while the core is in a system-wide profiling mode for event-based sampling.

8. A system comprising:
a memory; and
a processor to execute and retire a plurality of instructions for a virtual machine, the processor operatively coupled to the memory, wherein the processor comprises:
a reload register to store a plurality of reload values for different virtual machines, the plurality of reload values comprising a reload value for the virtual machine;
a performance monitoring counter (PMC) register coupled to the reload register;
an event-based sampler operatively coupled to the reload register and the PMC register, wherein the event-based sampler includes first circuitry to:
load the reload value of the virtual machine into the PMC register;
increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the plurality of instructions; and
upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value:
execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution; and
reload the reload value from the reload register into the PMC register.

9. The system of claim 8 , wherein the processor further comprises a processor tracer including second circuitry to capture trace data produced by execution of the plurality of instructions and to format the trace data as a plurality of trace data packets.

10. The system of claim 9 , wherein the processor further includes a memory buffer for use by the virtual machine, and the second circuitry is further to:
format the field data into a group of record packets corresponding to the elements;
interleave the group of record packets between ones of the plurality of trace data packets of the trace data, to generate a combined packet stream; and
store the combined packet stream in the memory buffer as a series of output pages.

11. The system of claim 10 , wherein the processor is further to generate a page fault when accessing a guest physical address for an output page of the series of output pages that is not mapped to a host physical address of the memory, and wherein a virtual machine monitor (VMM) is further to pause the virtual machine to handle the page fault.

12. The system of claim 10 , wherein the processor is further to execute a virtual machine monitor (VMM), and wherein to store the combined packet stream in the memory buffer as the series of output pages, the second circuitry is to:
while filling a first output page, prefetch a second output page;
test whether the second output page is mapped to a host physical page of the memory; and
trigger a virtual machine exit to request the VMM to map the second output page to the memory responsive to detecting that the second output page is not mapped to the memory.

13. The system of claim 9 , wherein the event-based sampler is further to execute the microcode to perform a series of signal operations that transmit the field data for the elements of the sampling record in a predetermined order to the processor tracer.

14. The system of claim 8 , further comprising a virtual machine control structure (VMCS) register, that when enabled, is to cause the event-based sampler to remain enabled upon exiting the virtual machine while the processor is in a system-wide profiling mode for event-based sampling.

15. A method comprising:
executing, by a processor core, a plurality of instructions for a virtual machine;
storing, by the processor core, a plurality of reload values for different virtual machines in a reload register, the plurality of reload values comprising a reload value for the virtual machine;
loading, by an event-based sampler into a performance monitoring counter (PMC) register, the reload value of the virtual machine;
incrementing, by the event-based sampler, the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the plurality of instructions;
upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler:
executing microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution; and
reloading the reload value from the reload register into the PMC register.

Assignees

• Intel Corp

Inventors

• Merten Matthew C
• Strong Beeman C
• Chynoweth Michael W
• Zhou Grant G
• Kleen Andreas
• Weier Kimberly C
• Schmid Angela D
• Bratanov Stanislav
• Abraham Seth
• Brandt Jason W
• Yasin Ahmad

Classifications

• G06F2201/86

  Event-based monitoring · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F11/3409

  for performance assessment · CPC title