Inspection method, inspection apparatus, and inspection program for disk-shaped graduation plate
US-2024212126-A1 · Jun 27, 2024 · US
US10495494B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10495494-B2 |
| Application number | US-201615736042-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 7, 2016 |
| Priority date | Jun 18, 2015 |
| Publication date | Dec 3, 2019 |
| Grant date | Dec 3, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method for detecting a short circuit to ground or to the operating voltage of a signal line ( 11, 12 ) of a resolver ( 16 ) has the following steps: —measuring the potential of the signal lines ( 13 a, 13 b; 14 a, 14 b ) of the receiver coil ( 18 ) with respect to ground at two sampling times (R and F) provided symmetrically at the middle of the excitation period; —calculating an offset value for a signal line pair ( 13 a, 13 b; 14 a, 14 b ) by calculating the average value of the four measured values (U HR , U LR , U HF and U LF ) for the associated receiver coil ( 17, 18 ); and —identifying a short circuit and the potential to which the short-circuited line is connected in that the offset value is compared to threshold values.
Opening claim text (preview).
The invention claimed is: 1. A method for detecting a short circuit ( 10 ) to ground or to the operating voltage (UB) of a signal line ( 11 , 12 ) of a resolver ( 16 ), having the following steps: measuring ( 31 ) the potential of the signal lines ( 13 a , 13 b ; 14 a , 14 b ) of the receiver coil with respect to ground at two sampling instants (R, F) which are situated symmetrically with respect to the midpoint of the excitation period; calculating ( 32 ) an offset value (UDC) for the respective signal line pair ( 13 a , 13 b ; 14 a , 14 b ) by forming the average of the four measured values (UHR, ULR, UHF, ULF) of the respective receiver coil ( 17 , 18 ); and identifying ( 33 ) a short circuit and the potential toward which the short-circuited line is able to be pulled, by comparing the offset value to limit values. 2. The method as claimed in claim 1 , wherein pull-up resistors (R 1 ; R 3 ) and pull-down resistors (R 2 ; R 4 ) which are connected to the signal lines ( 13 a , 13 b ; 14 a , 14 b ) are supplied with a voltage potential via their other end. 3. The method as claimed in claim 2 , wherein the voltage potentials of the pull-up resistors (R 1 ; R 3 ) and the pull-down resistors (R 2 ; R 4 ) differ from one another by a constant amount which is smaller than the measurement range of the A/D converters for the measured values of the receiver coil. 4. A circuit for detecting a short circuit of a signal line ( 11 , 12 ) of a resolver ( 16 ) to ground or to the operating voltage (UB), including: a control device ( 1 ) including a processor ( 2 ), power stages ( 3 , 4 ) and first terminals ( 6 , 7 ) for providing signals for excitation lines ( 11 , 12 ) to an excitation coil ( 16 ) of the resolver ( 15 ), and second terminals ( 7 a , 7 b , 8 a , 8 b ) for connecting signal lines ( 13 a , 13 b , 14 a , 14 b ) for the signals of a sine coil and a cosine coil ( 17 , 18 ); two A/D converters ( 21 , 22 ) which are connected to the second terminals ( 7 a , 7 b and 8 a , 8 b ) of the control device ( 1 ), the outputs of which being readable and evaluable by the software of the processor ( 2 ); the excitation lines ( 11 , 12 ) which couple the first terminals ( 5 , 6 ) of the excitation coil ( 16 ) to the resolver ( 15 ); the signal lines ( 13 a , 13 b , 14 a , 14 b ) which are to be diagnosed for the sine and cosine signals provided by the resolver ( 15 ), and which couple the resolver to the two terminals ( 7 a , 7 b , 8 a , 8 b ) of the control device ( 1 ); pull-up resistors (R 1 , R 3 ) which are connected via their one end to one of the terminals ( 7 a , 8 a ) for the conductors ( 13 a , 14 a ) sine coil ( 17 ) and of the cosine coil ( 18 ), and via their other end to a first DC voltage potential (UH); pull-down resistors (R 2 and R 4 ) which are connected via their one end to the other one of the terminals ( 7 b , 8 b ) for the lines ( 13 b , 14 b ) sine coil ( 17 ) and of the cosine coil ( 18 ), and which are connected via their other end to a second DC voltage potential (UL); four electronic switches ( 26 , 27 , 28 , 29 ) which are inserted into the connection of the terminals ( 7 a , 7 b ; 8 a , 8 b ) for the signal lines ( 13 a , 13 b ; 14 a , 14 b ) to inputs (H, L) of the A/D converters ( 21 , 22 ), wherein the switches ( 26 , 27 , 28 , 29 ) are configured such that they respectively disconnect one input of the A/D converter ( 21 , 22 ) from the signal line ( 13 a , 13 b ; 14 a , 14 b ) and temporarily connect this input to ground; and a display and/or storage device ( 9 ) for displaying and/or storing the information identified by the processor ( 2 ), into which the positive detection of a short circuit ( 10 ) of a signal line ( 11 , 12 ) of a resolver ( 16 ) to ground or to the operating voltage (UB) by the processor ( 2 ) is incorporated. 5. The circuit as claimed in claim 4 , wherein the pull-up resistors (R 1 and R 3 ) and pull-down resistors (R 2 and R 4 ) are integrated into the control device ( 1 ). 6. The circuit as claimed in claim 4 or 5 , wherein the resistance values of the pull-up resistors (R 1 and R 3 ) and pull-down resistors (R 2 and R 4 ) are large relative to the ohmic resistance of the sine coil ( 17 ) and the cosine coil ( 18 ). 7. A circuit for detecting a short circuit of a signal line ( 11 , 12 ) of a resolver ( 16 ) to ground or to the operating voltage (UB), including: a control device ( 1 ) including a processor ( 2 ), power stages ( 3 , 4 ) and first terminals ( 6 , 7 ) for providing signals for excitation lines ( 11 , 12 ) to an excitation coil ( 16 ) of the resolver ( 15 ), and second terminals ( 7 a , 7 b , 8 a , 8 b ) for connecting signal lines ( 13 a , 13 b , 14 a , 14 b ) for the signals of a sine coil and a cosine coil ( 17 , 18 ); two A/D converters ( 21 , 22 ) which are connected to the second terminals ( 7 a , 7 b and 8 a , 8 b ) of the control device ( 1 ), the outputs of which being readable and evaluable by the software of the processor ( 2 ); the excitation lines ( 11 , 12 ) which couple the first terminals ( 5 , 6 ) of the excitation coil ( 16 ) to the resolver ( 15 ); the signal lines ( 13 a , 13 b , 14 a , 14 b ) which are to be diagnosed for the sine and cosine signals provided by the resolver ( 15 ), and which couple the resolver to the two terminals ( 7 a , 7 b , 8 a , 8 b ) of the control device ( 1 ); pull-up resistors (R 1 , R 3 ) which are connected via their one end to one of the terminals ( 7 a , 8 a ) for the conductors ( 13 a , 14 a ) sine coil ( 17 ) and of the cosine coil ( 18 ), and via their other end to a first DC voltage potential (UH); pull-down resistors (R 2 and R 4 ) which are connected via their one end to the other one of the terminals ( 7 b , 8 b ) for the lines ( 13 b , 14 b ) sine coil ( 17 ) and of the cosine coil ( 18 ), and which are connected via their other end to a second DC voltage potential (UL); four additional A/D converters in which one input is set to ground, and the other inputs are connected to one of the terminals ( 7 a , 7 b , 8 a , 8 b ) for the signal lines ( 13 a , 13 b , 14 a , 14 b ) of the sine coil ( 17 ) and the cosine coil ( 18 ); and a display and/or storage device ( 9 ) for displaying and/or storing the information identified by the processor ( 2 ), into which the positive detection of a short circuit ( 10 ) of a signal line ( 11 , 12 ) of a resolver ( 16 ) to ground or to the operating voltage (UB) by the processor ( 2 ) is incorporated. 8. The circuit as claimed in claim 7 , wherein the pull-up resistors (R 1 and R 3 ) and pull-down resistors (R 2 and R 4 ) are integrated into the control device ( 1 ). 9. The circuit as claimed in claim 7 , wherein the resistance values of the pull-up resistors (R 1 and R 3 ) and pull-down resistors (R 2 and R 4 ) are large relative to the ohmic resistance of the sine coil ( 17 ) and the cosine coil ( 18 ).
for measuring angles or tapers; for testing the alignment of axes · CPC title
Testing or calibrating apparatus or arrangements provided for in groups G01D1/00 - G01D15/00 · CPC title
Linear or rotary variable differential transformers (LVDTs/RVDTs) having a single primary coil and two secondary coils · CPC title
Testing of circuits in sensor or actuator systems (testing of apparatus for measuring electric or magnetic variables G01R35/00; testing of indicating or recording apparatus G01D; in airbag systems B60R21/0173; checking gas analysers G01N33/007; monitoring or fail-safe circuits for electromagnets H01F7/1844) · CPC title
Physics · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.