Wiring board manufacturing method

Patent metadata

Field	Value
Publication number	US-10492291-B2
Application number	US-201715465895-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Mar 30, 2016
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.

First claim

What is claimed is:

1. A wiring board manufacturing method comprising:
forming a conductor pattern within a waste board section of a wiring board, the wiring board including a product section and the waste board section with the waste board section being provided on an outer periphery of the product section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged in a zigzag pattern, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and
selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.

2. The manufacturing method according to claim 1 ,
wherein, in the removing, the conductor at the apex of at least part of the plurality of polygonal lands is removed by drilling.

3. The manufacturing method according to claim 2 ,
wherein the wiring board includes a plurality of wiring layers in the product section and the waste board section, and
in the forming, the conductor pattern is included in at least two of the plurality of wiring layers.

4. The manufacturing method according to claim 3 ,
wherein, in the forming, a conductor pattern is included in at least one of the plurality of wiring layers, the conductor pattern in which the plurality of polygonal lands are arranged so as to be shifted in the first direction and the second direction with respect to the plurality of polygonal lands arranged on another wiring layer.

5. The manufacturing method according to claim 4 ,
wherein, in the removing, a conductor at the apex of at least part of the plurality of polygonal lands arranged on at least one of the wiring layers is removed by the drilling.

6. The manufacturing method according to claim 5 ,
wherein, in the removing, the conductor at the apex of at least part of the plurality of polygonal lands arranged on the other wiring layer is further removed by the drilling.

7. The manufacturing method according to claim 3 ,
wherein, in the forming,
a conductor pattern is formed in a first wiring layer of the plurality of wiring layers, the conductor pattern in which the plurality of polygonal lands are cyclically arranged along the first direction and the second direction,
a conductor pattern is formed on a second wiring layer of the plurality of wiring layers, the conductor pattern in which the plurality of polygonal lands are cyclically arranged so as to be shifted in the first direction and the second direction with respect to the plurality of polygonal lands arranged in the first wiring layer by a shift amount corresponding to a half of a repetition cycle of the plurality of polygonal lands,
a conductor pattern is formed on a third wiring layer of the plurality of wiring layers, the conductor pattern in which the plurality of polygonal lands are cyclically arranged so as to be shifted in the first direction and the second direction with respect to the plurality of polygonal lands arranged in the first wiring layer by a shift amount corresponding to a quarter of the repetition cycle of the plurality of polygonal lands, and
a conductor pattern is formed on a fourth wiring layer of the plurality of wiring layers, the conductor pattern in which the plurality of polygonal lands are cyclically arranged so as to be shifted in the first direction and the second direction with respect to the plurality of polygonal lands arranged in the first wiring layer by a shift amount corresponding to a third quarter of the repetition cycle of the plurality of lands, and
in the removing,
the conductor at the apex of at least part of the plurality of polygonal lands arranged on each of the first wiring layer to the fourth wiring layer is removed by forming through holes by the drilling.

8. The manufacturing method according to claim 1 ,
wherein each of the plurality of polygonal lands has a quadrangular shape.

9. The manufacturing method according to claim 1 ,
wherein each of the plurality of polygonal lands has a triangular shape.

10. A wiring board manufacturing method comprising:
forming a conductor pattern in a first wiring layer of a waste board section of a wiring board, the wiring board including a product section and the waste board section with the waste board section being provided on an outer periphery of the product section, and including a plurality of wiring layers in the product section and the waste board section, the conductor pattern in the first wiring layer including a slit in a zigzag pattern extending in a first direction; and
forming a conductor pattern on a second wiring layer of the waste board section, the conductor pattern in the second wiring layer including a slit in a zigzag pattern shifted in the first direction with respect to the zigzag pattern of the slit in the first wiring layer and extending in the first direction.

Assignees

• Fujitsu Ltd

Inventors

• Hiroshima Yoshiyuki
• Matsui Akiko
• Sugane Mitsuhiko
• Mukoyama Takahide
• Yamada Tetsuro
• Choraku Kohei

Classifications

• H05K2201/09263

  Meander · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K1/0271 Primary

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K2201/09418

  Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation · CPC title

• H05K2201/09381

  Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component · CPC title