System and method for rapid current sensing and transistor timing control

US10491096B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10491096-B2
Application numberUS-201715682940-A
CountryUS
Kind codeB2
Filing dateAug 22, 2017
Priority dateAug 22, 2017
Publication dateNov 26, 2019
Grant dateNov 26, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power electronics circuit is disclosed that includes a switching circuit comprising a first solid-state device coupled in series with a second solid-state device, with at least the first solid-state device comprising a solid-state switch having a gate terminal. The power electronics circuit also includes a current sense transformer positioned between the first and second solid-state devices and configured to sense a current flowing on a conductive trace connecting the first and second solid-state devices, and a controller coupled to the switching circuit and the current sense transformer so as to be in operable communication therewith. The controller is programmed to receive a current sense signal from the current sense transformer indicative of the current flowing on the conductive trace and modulate a gate voltage to the gate terminal of the first solid-state device based on the received current sense signal, so as to control switching thereof.

First claim

Opening claim text (preview).

What is claimed is: 1. A power electronics circuit comprising: a switching circuit comprising a first solid-state device coupled in series with a second solid-state device, with at least the first solid-state device comprising a first solid-state switch having a gate terminal; a current sense transformer positioned between the first and second solid-state devices and configured to sense a current flowing on a conductive trace connecting the first and second solid-state devices; a printed circuit board (PCB) having mounted thereon the switching circuit and the current sense transformer, and wherein the current sense transformer comprises: a plurality of planar conductive traces formed within the PCB; conductive pads formed on the surface of the PCB at locations corresponding to opposing ends of each of the plurality of planar conductive traces, so as to provide electrical connections to the plurality of planar conductive traces; and a plurality of conductive connectors coupled to the plurality of planar conductive traces to electrically and mechanically couple adjacent planar conductive traces together; and a controller coupled to the switching circuit and the current sense transformer so as to be in operable communication therewith, the controller programmed to: receive a current sense signal from the current sense transformer indicative of the current flowing on the conductive trace; and modulate a gate voltage to the gate terminal of the first solid-state device based on the received current sense signal, so as to control switching thereof. 2. The power electronics circuit of claim 1 wherein the plurality of conductive connectors comprise one of: pre-formed conductive staples coupled to the conductive pads on the surface of the PCB to connect the adjacent planar conductive traces; or Litz wires coupled to the conductive pads on the surface of the PCB to connect the adjacent planar conductive traces; with the conductive staples or Litz wires being through-hole mounted, soldered, or printed onto the conductive pads on the surface of the PCB. 3. The power electronics circuit of claim 1 wherein the switching circuit comprises a half-bridge circuit comprising the first solid-state switch and a second solid-state switch. 4. The power electronics circuit of claim 1 wherein the switching circuit comprises a diode-solid state switch series connection comprising the first solid-state switch and a diode. 5. The power electronics circuit of claim 1 wherein the first solid-state switch comprises one of a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (HEMT), an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), an integrated gate-commutated thyristor (IGCT), a gate turn-off (GTO) thyristor, or a silicon controlled rectifier (SCR). 6. The power electronics circuit of claim 1 wherein the first solid-state switch is formed of silicon carbide (SiC) or gallium nitride (GaN). 7. The power electronics circuit of claim 2 wherein the plurality of planar conductive traces and the plurality of conductive connectors collectively form a secondary transformer side in the current sense transformer, with the conductive trace connecting the first and second solid-state devices forming a primary transformer side. 8. A current sense transformer for sensing current in a power electronics circuit: a primary printed circuit board (PCB) trace formed on a substrate of a PCB, the primary PCB trace connecting a pair of solid-state devices positioned on the PCB; a plurality of planar conductive traces formed within one or more layers of the substrate of the PCB, so as to be positioned below the primary PCB trace; conductive pads formed on a surface of the substrate of the PCB at locations corresponding to opposing ends of each of the plurality of planar conductive traces to form pad mounted turns, the conductive pads providing electrical connections to the plurality of planar conductive traces; and a plurality of conductive connectors coupled to the plurality of planar conductive traces to electrically and mechanically couple adjacent planar conductive traces together, the plurality of conductive connectors extending over the primary PCB trace; wherein the primary PCB trace forms a primary side of the current sense transformer and the plurality of planar conductive traces, conductive pads, and plurality of conductive connectors form a secondary side of the current sense transformer. 9. The current sense transformer of claim 8 wherein the plurality of conductive connectors comprise pre-formed conductive staples or Litz wires coupled to the conductive pads on the surface of the PCB to connect the adjacent planar conductive traces. 10. The current sense transformer of claim 8 wherein the plurality of planar conductive traces and plurality of conductive connectors add minimal inductance to the power electronics circuit. 11. A method for performing current sensing and transistor timing control in a power conversion circuit that includes a first solid-state switching device and one of a second solid-state switching device and a diode, the method comprising: measuring, via a current sense transformer, a current flowing on a primary conductive trace of the power conversion circuit that connects the first solid-state switching device and the one of the second solid-state switching device and the diode; providing a current sense signal indicative of the current on the primary conductive trace to a controller; and modulating, via the controller, a gate voltage to a gate terminal of at least one of the first and second solid-state switching devices based on the received current sense signal, so as to control switching thereof; wherein modulating the gate voltage to the gate terminal of at least one of the first and second solid-state switching devices comprises: comparing the current sense signal to a pre-determined current threshold value; generating and applying a controlled voltage pulse signal to the gate terminal of the first solid-state switching device when the current sense signal exceeds the pre-determined current threshold value, so as to pull down and/or shape the gate voltage to the gate terminal; and modulating the gate voltage to the gate terminal of the first solid-state switching device without generating and applying a controlled voltage pulse signal when the current sense signal is below the pre-determined current threshold value. 12. The method of claim 11 further comprising: comparing a number of generated voltage pulse signals to a pre-determined threshold pulse count; declaring a fault condition in the power conversion circuit when the number of generated voltage pulse signals exceeds the pre-determined threshold pulse count; and implementing a circuit protection scheme upon declaration of the fault condition, so as to prevent a short circuit in the power conversion circuit. 13. The method of claim 11 further comprising: identifying a trend across a number of generated voltage pulse signals; and determining the health and/or estimating a remaining useful life of one or more components in the power conversion circuit based on the identified trend. 14. The method of claim 11 further comprising: tracking the number of generated controlled voltage pulse signals; and performing an analytics analysis of the tracked generated voltage pulse signals to determine a long-term switching control strategy for the first solid-state switching device. 15. A power electronics circuit comprising: a switching circuit comprising a first so

Assignees

Inventors

Classifications

  • Means for preventing simultaneous conduction of switches · CPC title

  • Non-printed inductor · CPC title

  • associated with surface mounted components · CPC title

  • Metal wires as connectors or conductors · CPC title

  • H02M1/08Primary

    Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

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Frequently asked questions

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What does patent US10491096B2 cover?
A power electronics circuit is disclosed that includes a switching circuit comprising a first solid-state device coupled in series with a second solid-state device, with at least the first solid-state device comprising a solid-state switch having a gate terminal. The power electronics circuit also includes a current sense transformer positioned between the first and second solid-state devices a…
Who is the assignee on this patent?
Gen Electric
What technology area does this patent fall under?
Primary CPC classification H02M1/08. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).