Memory check ASIC for fuzes and safety and arming devices

Patent metadata

Field	Value
Publication number	US-10490291-B1
Application number	US-201815961361-A
Country	US
Kind code	B1
Filing date	Apr 24, 2018
Priority date	Apr 24, 2018
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A memory check ASIC for fuzes and safety and arming (S&A) devices. The memory check ASIC may comprise: an ASIC, data line, clock line, shutdown line, and reset line. The ASIC may operatively couple to a microcontroller having a flash-based memory and may comprise: a digital logic for verifying a calculated checksum based on contents of the flash-based memory. A clock signal along with the calculated checksum may be transmitted to the ASIC via the clock line and data line, respectively. A shutdown signal may be transmitted from the ASIC to the microcontroller via the shutdown line in response to the verification of the calculated checksum by the digital logic. A reset signal may synchronize sampling of the calculated checksum and may be latched by flip-flop circuits of the digital logic for a predetermined number of clock cycles.

First claim

What is claimed as new and desired to be protected by Letters Patent is set forth in the appended claims:

1. A method for verifying contents of a flash-based memory of a microcontroller for fuzes and safety and arming (S&A) devices using a memory check application-specific integrated circuit (ASIC), said memory check ASIC comprising an ASIC operatively coupled to said microcontroller via at least: a data line, a clock line, and a shutdown line, said method comprising:
installing a resistor and a capacitor into a resistor terminal and a capacitor terminal of said ASIC, respectively, to configure a predetermined time interval of a timeout period;
wherein said resistor has a resistance between approximately 0.5 to 5 megaohms; and
wherein said capacitor has a capacitance between approximately 50 to 250 nanofarads;
monitoring, by said ASIC, said data line for a serial data in order to obtain a calculated checksum; and
transmitting a timeout signal by said ASIC via a timeout line when said microcontroller does not transmit said calculated checksum within said predetermined time interval of said timeout period.

2. A method for verifying contents of a flash-based memory of a microcontroller for fuzes and S&A devices using a memory check ASIC, said memory check ASIC comprising an ASIC operatively coupled to said microcontroller via at least: a data line, a clock line, and a shutdown line, said method comprising:
calculating, by said microcontroller, a checksum associated with said contents of said flash-based memory of said microcontroller;
communicating a serial data to said ASIC via said data line, said serial data including said calculated checksum;
monitoring, by said ASIC, said data line for said serial data in order to obtain said calculated checksum;
comparing, by a digital logic of said ASIC, said calculated checksum with a predetermined checksum to determine whether a checksum mismatch occurs, said checksum mismatch indicating invalid contents within said flash-based memory of said microcontroller; and
transmitting, by said ASIC via said shutdown line, a shutdown signal to said microcontroller, in response to said determination of said checksum mismatch;
wherein said ASIC comprises a reset line configured to receive a reset signal to synchronize sampling of said calculated checksum, said reset signal being latched by one or more flip-flop circuits of said digital logic and having a predetermined number of clock cycles.

Assignees

• Us Navy

Inventors

• Haddon Michael
• Duncan Jonathan

Classifications

• F42C15/40

  wherein the safety or arming action is effected electrically · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/3436 Primary

  Arrangements for verifying correct programming or erasure · CPC title

• F42B35/00 Primary

  Testing or checking of ammunition {(apparatus for measuring the energy of projectiles G01L5/14)} · CPC title