Array substrate and testing method and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10490109-B2
Application number	US-201314404180-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Aug 29, 2013
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

An array substrate, a testing method and a manufacturing method of the array substrate are disclosed. The array substrate comprises a first test line (3), a second test line (4), and first data lines (1) and second data lines (2) that are disposed alternately. The first data lines (1) are directly connected to the first test line (3), and the second data lines (2) are connected to the second test line (4) through switch elements (7); or, the second data lines (2) are directly connected to the second test line (4), and the first data lines (1) are connected to the first test line (3) through switch elements (7). With the array substrate, charges in the display region can be avoided from being transferred to a test line, thereby decreasing the accumulation of static electricity, and enhancing reliability of the short bar region.

First claim

The invention claimed is:

1. An array substrate, comprising a first test line, a second test line, switch elements, first data lines and second data lines,
wherein the first data lines and the second data lines are disposed alternately;
the first data lines are directly connected to the first test line, the second data lines are respectively connected to the switch elements which are connected to the second test line, and the switch elements are respectively configured to control a connection between the second data lines and the second test line; and
the array substrate further comprises a control line for the switch elements and the control line is connected to control ends of the switch elements.

2. The array substrate claimed as claim 1 , wherein the switch elements are first thin film transistors and the control ends are gate electrodes of the first thin film transistors.

3. The array substrate claimed as claim 1 , wherein the switch elements are first thin film transistors, the control ends are gate electrodes of the first thin film transistors; the first test line and the control line are of an integral structure.

4. The array substrate claimed as claim 2 , further comprising a gate metal layer and a source/drain metal layer;
wherein the control line is provided in a same layer as the gate metal layer, the second test line is connected to source electrodes of the first thin film transistors, and the second data lines are connected to drain electrodes of the first thin film transistors.

5. The array substrate claimed as claim 4 , wherein the second test line is provided in a same layer as the source/drain metal layer, the first data lines and the second data lines are provided in a same layer as the source/drain metal layer; the first test line is directly connected to the first data lines through via holes, and the second test line and source electrodes of the first thin film transistors are of an integral structure.

6. The array substrate claimed as claim 4 , wherein the second test line is provided in a same layer as the gate metal layer, the first data lines and the second data lines are provided in a same layer as the source/drain metal layer; the first test line is directly connected to the first data lines through via holes, and the second test line is connected to source electrodes of the first thin film transistors through via holes.

7. The array substrate claimed as claim 5 , wherein the control line and gate electrodes of the first thin film transistors are of an integral structure.

8. The array substrate claimed as claim 1 , further comprising second thin film transistors that are arranged in an array in a display region;
wherein the first thin film transistors and the second thin film transistors are of a same construction.

9. A method of testing the array substrate claimed as claim 1 , comprising:
inputting a data signal to the second test line, inputting no signal to the first test line and turning off the switch elements;
where the data signal is tested in a display region of the array substrate, it is determined that a short circuit happens between the first test line and the second test line.

10. A manufacturing method of an array substrate, comprising:
forming a first test line, a second test line, switch elements, first data lines and second data lines in a periphery region;
wherein the first data lines and second data lines disposed alternately;
the first data lines are directly connected to the first test line, the second data lines are respectively connected to the switch elements which are connected to the second test line, and the switch elements are respectively configured to control a connection between the second data lines and the second test line;
the manufacturing method further comprises forming a control line for the switch elements and the control line is connected to control ends of the switch elements.

11. The manufacturing method of the array substrate claimed as claim 10 , wherein the switch elements are first thin film transistors.

12. The manufacturing method of the array substrate claimed as claim 11 , comprising:
forming second thin film transistors in a display region as the first thin film transistors are formed.

13. The manufacturing method of the array substrate claimed as claim 12 , further comprising:
forming the first test line, a gate metal layer of the first thin film transistors and a gate metal layer of the second thin film transistors;
forming a gate insulating layer covering the entire base substrate;
forming an active layer of the first thin film transistors and an active layer of the second thin film transistors;
forming the first data lines, the second data lines, the second test line, and a source/drain metal layer of the first thin film transistors and a source/drain metal layer of the second thin film transistors;
forming a passivation layer and via holes.

14. The manufacturing method of the array substrate claimed as claim 12 , further comprising:
forming the first test line, the second test line, a gate metal layer of the first thin film transistors and a gate metal layer of the second thin film transistors;
forming a gate insulating layer covering the entire base substrate;
forming an active layer of the first thin film transistors and an active layer of the second thin film transistors;
forming the first data lines, the second data lines, the second test line, and a source/drain metal layer of the first thin film transistors and a source/drain metal layer of the second thin film transistors;
forming a passivation layer and via holes.

15. The manufacturing method of the array substrate claimed as claim 13 , wherein the control line and gate electrodes of the first thin film transistors are configured to be of an integral structure.

16. The manufacturing method of the array substrate claimed as claim 10 , wherein the control line and the first test line are of an integral structure.

17. The array substrate claimed as claim 3 , further comprising a gate metal layer and a source/drain metal layer;
wherein the control line is provided in a same layer as the gate metal layer, the second test line is connected to source electrodes of the first thin film transistors, and the second data lines are connected to drain electrodes of the first thin film transistors.

18. The array substrate claimed as claim 17 , wherein the second test line is provided in a same layer as the source/drain metal layer, the first data lines and the second data lines are provided in a same layer as the source/drain metal layer; the first test line is directly connected to the first data lines through via holes, and the second test line and source electrodes of the first thin film transistors are of an integral structure.

19. The array substrate claimed as claim 17 , wherein the second test line is provided in a same layer as the gate metal layer, the first data lines and the second data lines are provided in a same layer as the source/drain metal layer; the first test line is directly connected to the first data lines through via holes, and the second test line is connected to source electrodes of the first thin film transistors through via holes.

20. The array substrate claimed as claim 18 , wherein the control line and gate electrodes of the first thin film transistors are of an integral structure.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Li Liangliang
• Guo Zongjie
• Ding Xiangqian
• Liu Yao
• Bai Jinchao

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G02F1/1309

  Repairing; Testing · CPC title

• G01R31/28

  Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) · CPC title

• G02F2001/136254

  Physics · mapped topic