Memory address translation

Patent metadata

Field	Value
Publication number	US-10489304-B2
Application number	US-201715650056-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Jul 14, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

First claim

We claim:

1. Memory address translation apparatus comprising:
a translation data store to store one or more instances of translation data, where each instance of translation data provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space;
detector circuitry to detect whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data store;
in which the detector circuitry, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store:
retrieves a further instance of translation data that provides address range boundary values defining a further range of virtual memory addresses in the virtual memory address space, and indicates a translation between the virtual memory address in the further range of virtual address and a corresponding output memory address in the output address space, where the further range of virtual addresses includes the given virtual address; and
stores the further instance of the translation data in the translation data store; and

translation circuitry to apply the translation defined by a detected instance of the translation data to the given virtual memory address.

2. Apparatus according to claim 1 , in which the translation data of the one or more instances of translation data and the further instance of translation data indicates an address offset between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space.

3. Apparatus according to claim 1 , in which the translation data of the one or more instances of translation data and the further instance of translation data indicates a reference memory address in the output address space corresponding to a virtual memory address at a predetermined position relative to the range of virtual memory addresses, so that the translation circuitry is configured to translate the given virtual memory address in the range of virtual memory addresses by adding to or subtracting from the reference memory address in the output address space an amount dependent upon a difference, in the virtual memory address space, between the given virtual memory address and the virtual memory address at the predetermined position relative to the range of virtual memory addresses.

4. Apparatus according to claim 3 , in which:
the predetermined position is a lowest memory address in the range of virtual memory addresses.

5. Apparatus according to claim 1 , in which the detector is configured to access one or more memory locations storing further instances of the translation data.

6. Apparatus according to claim 5 , in which the detector is configured to retrieve one or more further instances of the translation data from memory locations defined by one or more location parameters indicating addresses in the output memory space.

7. Apparatus according to claim 5 , in which the detector is configured to retrieve the one or more further instances of the translation data in an order of usage of the instances of the translation data.

8. Apparatus according to claim 7 , in which the order of usage is an order of most frequent usage.

9. Apparatus according to claim 1 , in which each instance of translation data comprises administrative data indicating access permissions associated with the range of virtual memory addresses of that instance of translation data.

10. Data processing apparatus comprising:
a processor to process data in accordance with virtual memory addresses;
an address translation apparatus according to claim 1 , to translate a virtual memory address relating to a processing operation of the processor into an output memory address to access a memory system responsive to the output memory address.

11. Apparatus according to claim 10 , comprising a cache memory disposed between the address translation apparatus and the memory system, the cache memory being addressable in the output memory address space.

12. Apparatus according to claim 10 , in which:
the processor is responsive to context data defining a context applicable to a current task being executed by the processor; and
the context data includes location parameters indicating addresses in the output memory space at which one or more further instances of translation data are stored.

13. Apparatus according to claim 10 , comprising:
a memory system responsive to memory addresses in the output memory address space.

14. Apparatus according to claim 13 , comprising:
two or more processors to process data in accordance with virtual memory addresses in a respective virtual memory address space, each processor having a respective address translation apparatus to translate a virtual memory address relating to a processing operation of that processor into an output memory address to access the memory system.

15. Apparatus according to claim 14 , in which the memory system is configured to operate according to the output memory address space common to interaction with the address translation apparatus of each of the processors.

16. Apparatus according to claim 1 , comprising bypass logic to bypass the translation circuitry when the translation is such that a virtual memory address is equal to a corresponding output memory address.

17. Memory address translation apparatus comprising:
translation data storing means for storing one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space;
means for detecting whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data storing means;
in which the means for detecting, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data storing means:
retrieves a further instance of translation data that provides address range boundary values defining a further range of virtual memory addresses in the virtual memory address space, and indicates a translation between the virtual memory address in the further range of virtual address and a corresponding output memory address in the output address space, where the further range of virtual addresses includes the given virtual address; and
stores the further instance of translation data in the translation data storing means; and

translation means for applying the translation defined by a detected instance of the translation data to the given virtual memory address.

18. A memory address translation method comprising:
storing, in a translation data store, one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address bounda

Assignees

• Advanced Risc Mach Ltd

Inventors

• Beard Jonathan Curtis
• Rusitoru Roxana
• Dunham Curtis Glenn

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title