Flushing data content in response to a power loss event to a processor

Patent metadata

Field	Value
Publication number	US-10489237-B2
Application number	US-201415535669-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

In one example, a processor may include a processor core with a central processing unit as well as a processor cache separate from the processor core. The processor may also include flushing circuitry. The flushing circuitry may identify a power loss event for the processor. In response, the flushing circuitry may selectively power the processor by providing power to the processor cache but not to the processor core. The flushing circuitry may further flush data content of the processor cache to a non-volatile memory separate from the processor.

First claim

The invention claimed is:

1. A processor comprising:
a processor core that includes a central processing unit;
a processor cache separate from the processor core; and
flushing circuitry to:
identify a power loss event for the processor, the flushing circuitry to, in response to identifying the power loss event, perform both:
selectively power the processor by causing power to be provided to the processor cache but not to the processor core; and
flushing data content of the processor cache to a non-volatile memory separate from the processor.

2. The processor of claim 1 , wherein the flushing circuitry is to flush the data content of the processor cache to a non-volatile random access memory used by the processor during normal power operation.

3. The processor of claim 1 , further comprising a memory interface to the non-volatile memory; and
wherein the flushing circuitry is to selectively power the processor by further providing power to the memory interface.

4. The processor of claim 1 , wherein the flushing circuitry is further to scale the power provided to the processor cache according to a data capacity of the processor cache.

5. The processor of claim 1 , further comprising multiple power rails to supply power to the processor; and
wherein the flushing circuitry is to selectively power the processor by powering a particular power rail supplying power to the processor cache and not powering another power rail supplying power to the processor core.

6. The processor of claim 1 , wherein the processor comprises multiple processor caches accessible to the processor core; and
wherein the flushing circuitry is further to:
specifically identify the processor cache from among the multiple processor caches in the processor as storing a data state for the processor; and
flush the data content of the processor cache, but not data content of a different processor cache among the multiple processor caches.

7. The processor of claim 6 , wherein the flushing circuitry is to selectively power the processor further by not providing power to the different processor cache.

8. A method comprising:
identifying, by flushing circuitry, a power loss event for a processor;
selectively powering, by the flushing circuitry, part of the processor in response to the flushing circuitry identifying the power loss event by:
causing powering of a portion of the processor that includes a particular data buffer in the processor; and
not causing powering of another portion of the processor that includes a central processing unit of the processor; and

preserving, by the flushing circuitry, a data state of the processor by flushing data content from the particular data buffer to a non-volatile memory separate from the processor.

9. The method of claim 8 , wherein selectively powering part of the processor further comprises powering a memory interface to the non-volatile memory.

10. The method of claim 8 , wherein selectively powering part of the processor further comprises:
specifically identifying the particular data buffer from among multiple data buffers in the processor as storing the data state of the processor; and
not powering a different data buffer among multiple data buffers in the processor.

11. The method of claim 10 , wherein specifically identifying the particular data buffer from among multiple data buffers in the processor comprises determining that:
the different data buffers stores part, but not all, of the data state; and
the particular data buffer stores the data state of the processor.

12. A processor comprising:
a processor core portion that includes a central processing unit and a first processor cache;
a processor non-core portion that includes a second processor cache; and
flushing circuitry to:
determine that the second processor cache stores a data state for the processor; and
identify a power loss event for the processor, the flushing circuitry to, in response to identifying the power loss event, perform both:
selectively power the processor by causing power to be provided to the processor non-core portion that includes the second processor cache but not causing power to be provided to to the processor core portion; and
preserving a data state of the processor by flushing data content of the second processor cache to a non-volatile memory separate from the processor, but not flushing data content of the first processor cache.

13. The processor of claim 12 , wherein the flushing circuitry is further to scale the power provided to the second processor cache according to a data capacity of the second processor cache.

14. The processor of claim 12 , wherein the processor stores data according to a hierarchy of cache levels and wherein the second processor cache is a higher level than the first processor cache.

15. The processor of claim 12 , wherein the flushing circuitry is to flush the data content of the first processor cache to a non-volatile random access memory used by the processor during normal power operation.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Engler David
• Kapoor Mark
• Raymond Patrick

Classifications

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title