Storage device compatible with selected one of multiple interface standards

Patent metadata

Field	Value
Publication number	US-10489088-B2
Application number	US-201715675200-A
Country	US
Kind code	B2
Filing date	Aug 11, 2017
Priority date	Oct 24, 2016
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A storage device includes a nonvolatile semiconductor memory module, and a host interface for connection to a host that is external to the storage device. The host interface includes a first interface circuit conforming to Serial Peripheral Interface (SPI) and a second interface circuit conforming to an interface standard different from SPI. Output terminals of the first interface circuit are connected to input terminals of the second interface circuit, and output terminals of the second interface circuit are connected to input terminals of the nonvolatile semiconductor memory module.

First claim

What is claimed is:

1. A storage device comprising:
a nonvolatile semiconductor memory module; and
a host interface for connection to a host that is external to the storage device, the host interface including a first interface circuit conforming to Serial Peripheral Interface (SPI) and a second interface circuit conforming to an interface standard different from SPI, wherein
output terminals of the first interface circuit are connected to input terminals of the second interface circuit, and output terminals of the second interface circuit are connected to input terminals of the nonvolatile semiconductor memory module,
the first interface circuit includes first, second, and third terminals, and is configured to transmit, from the first terminal, as a command, an initial portion of a signal received through the second terminal after a chip select signal is received through the third terminal, and
the second interface circuit includes fourth, fifth, and sixth terminals, and is configured to transmit, from the fourth terminal, as a command, a portion of a signal received through the fifth terminal while a command latch enable signal received through the sixth terminal is asserted.

2. The storage device according to claim 1 , wherein
the nonvolatile semiconductor memory module and the host interface are formed on a substrate.

3. The storage device according to claim 1 , wherein
input terminals of the first interface circuit are directly connected to terminals of the storage device via wiring formed by wire bonding, and
input terminals of the second interface circuit are connected to the terminals of the storage device through the first interface circuit.

4. The storage device according to claim 3 , wherein
when a command is received through the host, both of the first and second interface circuit operate.

5. The storage device according to claim 1 , wherein
input terminals of the second interface circuit are directly connected to terminals of the storage device via wiring formed by wire bonding, and
input terminals of the first interface circuit are not connected to the terminals of the storage device.

6. The storage device according to claim 5 , wherein
when a command is received through the host, the second interface circuit operates, and the first interface circuit does not operate.

7. The storage device according to claim 1 , further comprising:
a switch circuit connected to terminals for connection to a host, and configured to transmit a command from the host to selected one of the first interface circuit and the second interface circuit.

8. The storage device according to claim 7 , wherein
the switch circuit is configured to switch between communication with the first interface circuit and communication with the second interface circuit, based on a command from the nonvolatile semiconductor memory module.

9. The storage device according to claim 7 , wherein
the nonvolatile semiconductor memory module, the switch circuit, and the host interface are formed on a substrate.

10. The storage device according to claim 7 , wherein
input terminals of the switch circuit are connected to terminals of the storage device via wiring formed by wire bonding, and
output terminals of the switch circuit include terminals connected to input terminals of the first interface circuit and terminals connected to input terminals of the second interface circuit.

11. The storage device according to claim 1 , wherein the first terminal is connected to the fifth terminal.

12. The storage device according to claim 1 , wherein
the second interface circuit conforms to an interface of a NAND flash memory.

13. A method for manufacturing a storage device, comprising:
forming a nonvolatile semiconductor memory module; and
forming a host interface for connection to a host that is external to the storage device, the host interface including a first interface circuit conforming to Serial Peripheral Interface (SPI) and a second interface circuit conforming to an interface standard different from SPI, wherein
the first interface circuit includes first, second, and third terminals, and is configured to transmit, from the first terminal, as a command, an initial portion of a signal received through the second terminal after a chip select signal is received through the third terminal, and
the second interface circuit includes fourth, fifth, and sixth terminals, and is configured to transmit, from the fourth terminal, as a command, a portion of a signal received through the fifth terminal while a command latch enable signal received through the sixth terminal is asserted; and

connecting output terminals of the first interface circuit to input terminals of the second interface circuit;
connecting output terminals of the second interface circuit to input terminals of the nonvolatile semiconductor memory module; and
connecting directly selected one of (i) input terminals of the first interface circuit and (ii) input terminals of the second interface circuit, to terminals of the storage device for connection to the host, via wiring by wire bonding.

14. The method according to claim 13 , wherein
the nonvolatile semiconductor memory module and the host interface are formed on a substrate.

15. The method according to claim 13 , wherein
the input terminals of the first interface circuit are directly connected to the terminals of the storage device via the wiring.

16. The method according to claim 13 , wherein
the input terminals of the second interface circuit are directly connected to the terminals of the storage device via the wiring.

17. The method according to claim 13 , wherein
the second interface circuit conforms to an interface of a NAND flash memory.

18. The method according to claim 13 , further comprising:
storing setting data conforming to the first interface circuit in a storage of the nonvolatile semiconductor memory module, when the first interface circuit is selected; and
storing setting data conforming to the second interface circuit in the storage of the nonvolatile semiconductor memory module, when the second interface circuit is selected.

Assignees

• Toshiba Memory Corp

Inventors

• Kodera Shunsuke
• Furuyama Yoshio

Classifications

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0661

  Format or protocol conversion arrangements · CPC title

• G06F3/0605

  by facilitating the interaction with a user or administrator · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title