Systems and methods for storing information

Patent metadata

Field	Value
Publication number	US-10489067-B2
Application number	US-201715487975-A
Country	US
Kind code	B2
Filing date	Apr 14, 2017
Priority date	Oct 15, 2012
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

An information storage circuit having a first memory portion configured to store a first validity bit and first data; a second memory portion configured to store a second validity bit and second data; and a subcircuit configured to: write the first data to the first memory portion and the second data to the second memory portion sequentially; and set the first and second validity bits to indicate which of the first data and second data is valid.

First claim

What is claimed is:

1. An information storage circuit, comprising:
a first memory configured to store a first validity bit and first data;
a first supply domain coupled to the first memory and configured to supply power to the first memory via at least a first capacitor during power loss;
a second memory configured to store a second validity bit and second data;
a second supply domain coupled to the second memory and configured to supply power to the second memory via at least a second capacitor during power loss, the first capacitor being different from the second capacitor;
a subcircuit configured to:
set the first validity bit of the first memory to invalid,
write the first data to the first memory while the first validity bit is set to invalid, and
reset the first validity bit of the first memory as valid, indicating that the written first data is valid,
wherein the subcircuit is configured to write the first data to the first memory and the second data to the second memory sequentially; and

a logic configured to determine during a start-up the settings of the first and second validity bits.

2. The information storage circuit of claim 1 , wherein the subcircuit is configured to write the first and second data to the first and second memories, respectively, one at a time.

3. The information storage circuit of claim 1 , wherein valid data is stored in at least one of the first and second memories.

4. The information storage circuit of claim 3 , wherein the subcircuit is configured to:
set the second validity bit of the second memory to be invalid,
write the second data to the second memory while the second validity bit is set to invalid, and
reset the second validity bit of the second memory be valid, indicating that the written second data is valid.

5. The information storage circuit of claim 4 , wherein the subcircuit is configured to:
reset the first validity bit to valid after the writing of the first data is complete, and
reset the second validity bit to valid after the writing of the second data is complete.

6. The information storage circuit of claim 4 , wherein the subcircuit is configured to:
repeat in order the setting the first validity bit to invalid, the writing the first data, the resetting the first validity bit to valid, the setting the second validity bit to invalid, the writing the second data, and the resetting the second validity bit to valid.

7. The information storage circuit of claim 1 , wherein the subcircuit is configured to set the first validity bit to valid after the writing of the first data is complete.

8. The information storage circuit of claim 7 , wherein if a loss of power or interruption occurs during the writing step, the first validity bit for the first memory is not valid.

9. The information storage circuit of claim 1 ,
wherein if the first or second validity bit is set to invalid, at a next start-up, the subcircuit is configured to:
check the first or second validity bit that was set to invalid; and
reset the first or second memory, which corresponds with the first or second validity bit that was set to invalid, and

wherein the first or second data of the other of the first and second memories, respectively, is valid.

10. A method for storing information in first and second memories configured to store first and second validity bits, respectively, the method comprising:
by a first supply domain coupled to the first memory, supplying power to the first memory via at least a first capacitor during power loss;
by a second supply domain coupled to the second memory, supplying power to the second memory via at least a second capacitor during power loss, the first capacitor being different from the second capacitor;
setting the first validity bit of the first memory to invalid;
writing first data to the first memory while the first validity bit is set to invalid;
resetting the first validity bit of the first memory to valid, indicating that the written first data is valid,
wherein valid data is stored in at least one of the first and second memories; and
determining, by a logic during a start-up, the settings of the first and second validity bits.

11. The method of claim 10 , wherein the first and second memories are written to one at a time.

12. The method of claim 10 , wherein the first validity bit is reset to valid after the writing of the first data is complete.

13. The method of claim 12 , wherein if a loss of power or interruption occurs during the writing step, the first validity bit for the first memory is not valid.

14. The method of claim 10 , further comprising:
setting the second validity bit of the second memory to invalid;
writing the second data to the second memory while the second validity bit is set to invalid; and
resetting the second validity bit of the second memory to valid, indicating that the written second data is valid.

15. The method of claim 14 , wherein:
the first validity bit is reset to valid after the writing of the first data is complete, and
the second validity bit is reset to valid after the writing of the second data is complete.

16. The method of claim 14 , repeating in order the steps of setting the first validity bit to invalid, the writing the first data, the resetting the first validity bit to valid, the setting the second validity bit to invalid, the writing the second data, and the resetting the second validity bit to valid.

17. The method of claim 10 , wherein if the first or second validity bit is set to invalid, at a next start-up, further comprising:
checking the first or second validity bit that was set to invalid; and
resetting the first or second memory, which corresponds with the first or second validity bit that was set to invalid,
wherein the first or second data of the other of the first and second memories, respectively, is valid.

Assignees

• Infineon Technologies Ag

Inventors

• Ionescu Mihai-Alexandru
• Schroers Christoph
• Cassata Davide
• Fischer Hubert
• Horn Wolfgang
• Mialtu Razvan-Catalin
• Mihaescu Radu

Classifications

• G06F3/064

  Management of blocks · CPC title

• G01D3/022

  having an ideal characteristic, map or correction data stored in a digital memory · CPC title

• G01D18/008

  with calibration coefficients stored in memory · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G01D9/06

  Multiple recording, e.g. duplicating · CPC title