Multilayer ceramic substrate

Patent metadata

Field	Value
Publication number	US-10485099-B2
Application number	US-201816170427-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Apr 28, 2016
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A multilayer ceramic substrate according to the present invention includes a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material, a plurality of first constraint layers which contain a metal oxide not completely sintered at the sintering temperature of the low-temperature co-fired ceramic material and which are located between the base layers, and a protective layer which contains the metal oxide and which is in contact with an outermost base layer of the plurality of base layers in the lamination direction, and wherein X1>X2, where X1 is a content of the metal oxide in a surface section of the protective layer and X2 is a content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer.

First claim

The invention claimed is:

1. A multilayer ceramic substrate comprising:
a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material;
a plurality of first constraint layers which contain a metal oxide that is not completely sintered at a sintering temperature of the low-temperature co-fired ceramic material and which are located between adjacent base layers of the plurality of laminated base layers; and
a protective layer which contains the metal oxide and which is located outermost in a lamination direction of the plurality of laminated base layers and is in contact with an outermost base layer of the plurality of laminated base layers in the lamination direction,
wherein X1>X2, where X1 is a first content of the metal oxide in a surface section of the protective layer and X2 is a second content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer, and
wherein the protective layer includes a second constraint sublayer in contact with the outermost base layer and a covering ceramic sublayer on the second constraint sublayer, and multilayer ceramic substrate further comprises a wiring conductor on the second constraint sublayer, the covering ceramic sublayer is located so as to cover a periphery of the wiring conductor on the second constraint sublayer, the covering ceramic sublayer contains the metal oxide, and a surface of the covering ceramic sublayer has a region having a metal oxide content higher than that of other regions of the covering ceramic sublayer.

2. The multilayer ceramic substrate according to claim 1 , wherein α 11 <α 22 , where α 11 is a first thermal expansion coefficient of the surface section of the protective layer and α 22 is a second thermal expansion coefficient of the boundary section of the protective layer.

3. The multilayer ceramic substrate according to claim 1 , wherein the protective layer includes an outermost sublayer located outermost in the lamination direction, the second constraint sublayer and the outermost sublayer contain the metal oxide, and x1>x2 is satisfied, where x1 is a first content of the metal oxide in the outermost sublayer and x2 is a second content of the metal oxide in the second constraint sublayer.

4. The multilayer ceramic substrate according to claim 3 , wherein α 12 <α 23 , where α 12 is a first thermal expansion coefficient of the outermost sublayer and α 23 is a second thermal expansion coefficient of the second constraint sublayer.

5. The multilayer ceramic substrate according to claim 1 , wherein the covering ceramic sublayer contains a second low-temperature co-fired ceramic material.

6. The multilayer ceramic substrate according to claim 1 , wherein the protective layer is composed of only the second constraint sublayer in contact with the outermost base layer.

7. The multilayer ceramic substrate according to claim 6 , wherein the region of the second constraint sublayer has a thermal expansion coefficient less than that of the other regions of the second constraint sublayer.

8. The multilayer ceramic substrate according to claim 1 , wherein the region of the covering ceramic sublayer has a thermal expansion coefficient less than that of the other regions of the covering ceramic sublayer.

9. The multilayer ceramic substrate according to claim 1 , wherein X1>X3>X2, where X3 is a third content of the metal oxide in a central section of the protective layer.

10. The multilayer ceramic substrate according to claim 1 , wherein α 22 <β, where α 22 is a first thermal expansion coefficient of the boundary section of the protective layer, and β is a second thermal expansion coefficient of the base layer.

11. The multilayer ceramic substrate according to claim 1 , wherein the metal oxide is at least one of alumina and silica.

12. The multilayer ceramic substrate according to claim 1 , further comprising a second wiring conductor in or on at least one of the outermost base layer, the first constraint layers, and the protective layer.

13. The multilayer ceramic substrate according to claim 1 , wherein the low-temperature co-fired ceramic material is selected from glass composite low-temperature co-fired ceramic materials, crystal glass low-temperature co-fired ceramic materials, and non-glass low-temperature co-fired ceramic materials.

14. The multilayer ceramic substrate according to claim 1 , wherein the metal oxide includes at least one of aluminum, silica, zirconia, titania, silica, niobium pentoxide, tantalum pentoxide, and magnesia.

15. The multilayer ceramic substrate according to claim 1 , wherein the first metal oxide contained in the first constraint layers and the second metal oxide contained in the protective layer are the same.

16. A multilayer ceramic substrate comprising:
a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material;
a plurality of first constraint layers which contain a metal oxide that is not completely sintered at a sintering temperature of the low-temperature co-fired ceramic material and which are located between adjacent base layers of the plurality of laminated base layers; and
a protective layer which contains the metal oxide and which is located outermost in a lamination direction of the plurality of laminated base layers and is in contact with an outermost base layer of the plurality of laminated base layers in the lamination direction,
wherein X1>X2, where X1 is a first content of the metal oxide in a surface section of the protective layer and X2 is a second content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer, and
wherein α 11 <α 33 <α 22 , where α 11 is a first thermal expansion coefficient of the surface section of the protective layer, α 22 is a second thermal expansion coefficient of the boundary section of the protective layer, and α 33 is a third thermal expansion coefficient of the central section of the protective layer.

17. A multilayer ceramic substrate comprising:
a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material;
a plurality of first constraint layers which contain a metal oxide that is not completely sintered at a sintering temperature of the low-temperature co-fired ceramic material and which are located between adjacent base layers of the plurality of laminated base layers; and
a protective layer which contains the metal oxide and which is located outermost in a lamination direction of the plurality of laminated base layers and is in contact with an outermost base layer of the plurality of laminated base layers in the lamination direction,
wherein X1>X2, where X1 is a first content of the metal oxide in a surface section of the protective layer and X2 is a second content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer, and
wherein X2>Y, where Y is a third content of the metal oxide in the base layer.

Assignees

• Murata Manufacturing Co

Inventors

• Oka Takahiro
• Yamagami Yoshitake
• Takemori Yuki
• Kishida Kazuo
• Kawakami Hiromichi

Classifications

• H05K3/46

  Manufacturing multilayer circuits · CPC title

• H05K2201/068

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• H05K2201/0195

  Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure · CPC title

• H05K2201/0175

  Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor · CPC title

• H05K1/0271 Primary

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title