Decoding method and decoder for low-density parity-check code

Patent metadata

Field	Value
Publication number	US-10484009-B2
Application number	US-201815982503-A
Country	US
Kind code	B2
Filing date	May 17, 2018
Priority date	Nov 17, 2015
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A decoding method and a decoder for a low-density parity-check (LDPC) code, where the method includes dividing, by a decoder, an LDPC code C whose bit length is n into k LDPC codes D={D 1 ,D 2 ,K,D k-1 ,D k }, arranging, by the decoder, D i , i=1,2,K,k−1,k by column to obtain transpose codes D T ={D 1 T ,D 2 T ,K,D k-1 T ,D k T } of the LDPC codes D, performing cyclic shift on D i T ,i=1,2,K,k−1,k by row according to values of corresponding elements in a target check matrix to obtain shift codes E={E 1 ,E 2 ,K,E t-1 ,E t }, where t is equal to a quantity of rows of the target check matrix, obtaining, by the decoder, t*m groups of LDPC subcodes F 1 ,F 2 ,K,F tm-1 ,F tm according to the shift codes E and a bit length d of the decoder, where E j is divided into m groups, E j ={(E j ) 1 d ,(E j ) d+1 2d ,K,(E j ) (m-2)d+1 (m-1)d ,(E j ) (m-1)d+1 md }={F (j-1)m+1 ,F (j-1)m+2 ,K,F jm-1 ,F jm }, and m=┌l/d┐, and decoding, by the decoder, the m groups of LDPC subcodes to obtain a decoding result of the LDPC code C.

First claim

What is claimed is:

1. A decoding method for a low-density parity-check (LDPC) code, comprising:
dividing, by a decoder, an LDPC code C whose bit length is n into k divided LDPC codes D, the LDPC code C={c 1 ,c 2 ,c 3 ,K,c n-1 ,c n }, the divided LDPC codes D={D 1 ,D 2 ,K,D k-1 ,D k }, D i ={c (i-1)l+1 ,c (i-1)l+2 ,K,c il-1 ,c il }i=1,2,K,k−1,k, and a bit length of the D i comprising l=n/k;
arranging, by the decoder, the D i ,i=1,2,K,k−1,k by column to obtain transpose codes (D T ) of the divided LDPC codes D, the D T ={D 1 T ,D 2 T ,K,D k-1 T ,D k T }, D i T ={c (i-1)l+1 ,c (i-1)l+2 ,K,c il-1 ,c il } T , and i=1,2,K,k−1,k;
performing, by the decoder, cyclic shift on the D i T ,i=1,2,K,k−1,k by row according to values of corresponding elements in a target check matrix to obtain shift codes (E), the E={E 1 ,E 2 ,K,E t-1 ,E t }, t being equal to a quantity of rows of the target check matrix, E j comprising a result of shifting the D T according to an element of a j th row in the target check matrix, and j=1,2,K,t−1,t;
obtaining, by the decoder, t*m groups of LDPC subcodes according to the E and a bit length of the decoder (d), the LDPC subcodes comprising F 1 ,F 2 ,K,F tm-1 ,F tm , the E j being divided into m groups, the E j ={(E j ) 1 d ,(E j ) d+1 2d ,K,(E j ) (m-2)d+1 (m-1)d ,(E j ) (m-1)d+1 md }={F (j-1)m+1 ,F (j-1)m+2 ,K,F jm-1 ,F jm }, (E j ) (s-1)d+1 sd , s=1,2,K, m−1,m denoting an [(s−1)d+1] th row to an (sd) th row of the E j , and m=┌l/d┐; and
decoding, by the decoder, m groups of the LDPC subcodes to obtain a decoding result of the LDPC code C such that a quantity of parallel decoding operations on the LDPC code C being controlled flexibly.

2. The method of claim 1 , wherein decoding the m groups of the LDPC subcodes to obtain the decoding result of the LDPC code C comprises:
obtaining, by the decoder, log likelihood ratio (LLR) values corresponding to the LDPC subcodes, the LLR values corresponding to the LDPC subcodes comprising G 1 ,G 2 ,K,G tm-1 ,G tm ;
updating, by the decoder, check nodes according to the LLR values in an order of r=1,2,K,tm−1,tm to obtain a row-updated matrix;
updating, by the decoder, variable nodes column by column according to the row-updated matrix to obtain a column-updated matrix; and
performing, by the decoder, decision and checking on the column-updated matrix to obtain the decoding result of the LDPC code C.

3. The method of claim 1 , wherein the LDPC code C comprises a quasi-cyclic LDPC (QC-LDPC) code, and the l comprising an inflation factor of the QC-LDPC code.

4. The method of claim 1 , wherein the d comprises sixty.

5. The method of claim 1 , wherein decoding the m groups of the LDPC subcodes to obtain the decoding result of the LDPC code C comprises decoding, by the decoder, the m groups of the LDPC subcodes using a minimum sum (Min-sum) decoding algorithm to obtain the decoding result of the LDPC code C.

6. The method of claim 1 , wherein the d comprises one hundred eighty.

7. A decoder for a low-density parity-check (LDPC) code, comprising:
a memory comprising instructions; and
a processor coupled to the memory, the instructions causing the processor to be configured to:
divide an LDPC code C whose bit length is n into k divided LDPC codes D, the LDPC code C={c 1 ,c 2 ,c 3 ,K,c n-1 ,c n }, the divided LDPC codes D={D 1 ,D 2 ,K,D k-1 ,D k }, D i ={c (i-1)l+1 ,c (i-1)l+2 ,K,c il-1 ,c il }, i=1,2,K,k−1,k, and a bit length of the D i comprising l=n/k;
arrange the D i ,i=1,2,K,k−1,k by column to obtain transpose codes (D T ) of the divided LDPC codes D, the D T ={D 1 T ,D 2 T ,K,D k-1 T ,D k T }, D i T ={c (i-1)l+1 ,c (i-1)l+2 ,K, c il-1 , c il } T , and i=1,2,K,k−1,k;
perform cyclic shift on the D i T ,i=1,2,K,k−1,k by row according to values of corresponding elements in a target check matrix to obtain shift codes (E), the E={E 1 ,E 2 ,K,E t-1 , E t }, t being equal to a quantity of rows of the target check matrix, and E j comprising a result of shifting the D T according to an element of a j th row in the target check matrix, and j=1,2,K,t−1,t;
obtain t*m groups of LDPC subcodes according to the E and a bit length of the decoder (d), the E j being divided into m groups, the E j ={(E j ) 1 d ,(E j ) d+1 2d ,K,(E j ) (m-2)d+1 (m-1)d ,(E j ) (m-1)d+1 md }={F (j-1)m+1 ,F (j-1)m+2 ,K,F jm-1 ,F jm }, (E j ) (s-1)d+1 sd , s=1,2,K, m−1,m denoting an [(s−1)d+1] th row to an (sd) th row of the E j , and m=┌l/d┐; and
decode m groups of the LDPC subcodes to obtain a decoding result of the LDPC code C such that a quantity of parallel decoding operations on the LDPC code C being controlled flexibly.

8. The decoder of claim 7 , wherein the instructions further cause the processor to be configured to:
obtain log likelihood ratio (LLR) values corresponding to the LDPC subcodes, the LLR values corresponding to the LDPC subcodes comprising G 1 ,G 2 ,K,G tm-1 ,G tm ;
update check nodes according to the LLR values in an order of r=1,2,K,tm−1,tm to obtain a row-updated matrix;
update variable nodes column by column according to the row-updated matrix to obtain a column-updated matrix; and
perform decision and checking on the column-updated matrix to obtain the decoding result of the LDPC code C.

9. The decoder of claim 7 , wherein the LDPC code C comprises a quasi-cyclic LDPC (QC-LDPC) code, and the l comprising an inflation factor of the QC-LDPC code.

10. The decoder of claim 7 , wherein the d comprises sixty.

11. The decoder of claim 7 , wherein the instructions further cause the processor to be configured to decode the m groups of the LDPC subcodes using a minimum sum (Min-sum) decoding algorithm to obtain the decoding result of the LDPC code C.

12. The decoder of claim 7 , wherein the d comprises one hundred eighty.

13. A computer program product comprising a non-transitory computer readable storage medium storing program code thereon for decoding a low-density parity-check (LDPC) code, the program code comprising instructions for executing a method that comprises:
dividing, by a decoder, an LDPC code C whose bit length is n into k divided LDPC codes D, the LDPC code C={c 1 ,c 2 ,c 3 ,K,c n-1 ,c n }, the divided LDPC codes D={D 1 ,D 2 ,K,D k-1 ,D k }, D i ={c (i-1)l+1 ,c (i-1)l+2 ,K,c il-1 ,c il }, i=1,2,K,k−1,k, and a bit length of the D i comprising l=n/k;
arranging, by the decoder, the D i ,i=1,2,K,k−1,k by column to obtain transpose codes (D T ) of the divided LDPC codes D, the D T ={D 1 T ,D 2 T ,K,D k-1 T ,D k T }, D i T ={c (i-1)l+1 ,c (i-1)l+2 ,K,c il-1 ,c il } T ,i=1,2,K,k−1,k;
performing, by the decoder, cyclic shift on the D i T i=1,2K,k−1,k by row according to values of corresponding elements in a target check matrix to obtain shift codes (E), the E={E 1 ,E 2 ,K,E t-1 ,t}, t being equal to a quantity of rows of the target check matrix, E j comprising a result of shifting the D T according to an element of a j th row in the target check matrix, and j=1,2,K,t−1,t;
obtaining, by the decoder, t*m groups of LDPC subcodes according to the E and a bit length of the decoder (d), the LDPC subcodes comprising F 1 ,F 2 ,K,F tm-1 ,F tm , the E j being divided into m groups, the E j ={(E j ) 1 d ,(E j ) d+1 2d ,K,(E j ) (m-2)d+1 (m-1)d ,(E j ) (m-1)d+1 md }={F (j-1)m+1 ,F (j-1)m+2 ,K,F jm-1 ,F jm }, (E j ) (s-1)d+1 sd , s=1,2,K,m−1,m denoting an [(s−1)d+1] th row to an (sd) th row of the E j , and m=┌l/d┐; and
decoding, by the decoder, m groups of the LDPC subcodes to obtain a decoding result of the LDPC code C such that a quantity of parallel decoding operations on the LDPC code C being controlled flexibly.

Assignees

• Huawei Tech Co Ltd

Inventors

• Fan Jiaqi
• Si Xiaoshu

Classifications

• H03M13/1117

  using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule · CPC title

• H03M13/6508

  Flexibility, adaptability, parametrability and configurability of the implementation · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H03M13/112 Primary

  with correction functions for the min-sum rule, e.g. using an offset or a scaling factor · CPC title

• H03M13/116

  Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices · CPC title