Power converter system
US-2024364218-A1 · Oct 31, 2024 · US
US10483847B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10483847-B2 |
| Application number | US-201514601401-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 21, 2015 |
| Priority date | Mar 9, 2010 |
| Publication date | Nov 19, 2019 |
| Grant date | Nov 19, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Methods and apparatus for a power regulator according to various aspects of the present invention may comprise a sensor adapted to generate a measurement of a voltage or a current. A memory may store a correction parameter that corresponds to the measurement, and a correction system may be adapted to adjust the measurement according to the correction parameter.
Opening claim text (preview).
What is claimed is: 1. A power regulator, comprising: a sensor configured to generate a first measurement comprising at least one of a voltage measurement and a current measurement; a memory configured to store a correction parameter associated with the first measurement; a correction system configured to adjust the first measurement according to the correction parameter; a power stage; a controller configured to regulate an output of the power regulator according to the adjusted first measurement, wherein the controller comprises a PWM (pulse width modulation) circuit configured to provide, to the power stage, a duty cycle based upon the adjusted first measurement. 2. The power regulator of claim 1 , further comprising a test interface configured to receive the correction parameter from a test system and to write the correction parameter to the memory. 3. The power regulator of claim 2 , wherein the test interface is configured to allow the test system to control the output of the power regulator. 4. The power regulator of claim 2 , wherein the test interface is configured to transmit the first measurement to the test system. 5. The power regulator of claim 2 , wherein the controller is configured to operate in an operating mode which comprises: a normal mode; and a test mode. 6. The power regulator of claim 5 , wherein the test interface is further configured to receive an operating mode signal from the test system and place the power regulator into a corresponding operating mode. 7. The power regulator of claim 6 , wherein the correction parameter comprises a first correction parameter for a first operating mode and a second correction parameter for a second operating mode. 8. The power regulator of claim 1 , wherein the sensor comprises a current sensor associated with an error, and wherein the correction parameter is adapted to compensate for the error. 9. The power regulator of claim 1 , further comprising a voltage sensor associated with an error, wherein the correction parameter is adapted to compensate for the error. 10. The power regulator of claim 1 , wherein the correction parameter comprises a voltage sense offset. 11. The power regulator of claim 1 , wherein the correction parameter comprises a current sense offset and a gain adjustment for each mode of operation. 12. The power regulator of claim 1 , wherein the correction parameter comprises an offset and a gain adjustment for the power stage and an additional offset and an additional gain adjustment for an additional power stage of the power regulator. 13. The power regulator of claim 1 , wherein the correction parameter comprises a look up table comprising a plurality of non-linear corrections of a current sense transfer function. 14. The power regulator of claim 1 , wherein the power regulator comprises a buck converter. 15. The power regulator of claim 1 , wherein the power stage of the power regulator comprises a metal-oxide semiconductor field-effect transistor (MOSFET). 16. The power regulator of claim 8 , further comprising an output inductor, wherein the current sensor is a direct-current resistance (DCR) sensor that uses a voltage across the output inductor to sense a current in the output inductor. 17. The power regulator of claim 8 , wherein the power stage further comprises a transistor, and the current sensor uses a voltage across a drain and a source terminal of the transistor to measure a current in the transistor. 18. The power regulator of claim 8 , wherein the power stage further comprises a transistor, and the current sensor comprises a current mirror of the transistor. 19. The power regulator of claim 8 , further comprising a resistor coupled to an input, the output, or a ground return of the power regulator, and the current sensor uses a voltage across the resistor to determine the first measurement.
for trimming or tuning of electrical components · CPC title
with a plurality of power processing stages connected in parallel · CPC title
with automatic control of output voltage or current, e.g. switching regulators · CPC title
Testing power supplies (testing photovoltaic devices H02S50/10) · CPC title
Arrangements for measuring currents or voltages or for indicating presence or sign thereof (G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.