Semiconductor structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10483371-B2
Application number	US-201815925974-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 21, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dielectric barrier layer structure on the gate dielectric layer, a first silicon source gas being used to dope silicon in the dielectric barrier layer structure; forming a work function layer on the dielectric barrier layer structure; forming a gate barrier layer structure on the work function layer, a second silicon source gas being used to dope silicon in the gate barrier layer structure; and forming a gate electrode layer on the gate barrier layer structure.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a gate dielectric layer on the substrate;
forming a dielectric barrier layer structure on the gate dielectric layer, wherein a first silicon source gas is used to dope silicon in the dielectric barrier layer structure;
forming a work function layer on the dielectric barrier layer structure;
forming a gate barrier layer structure on the work function layer, wherein a second silicon source gas is used to dope silicon in the gate barrier layer structure, wherein the dielectric barrier layer structure has a stacked structure and an average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than an average atomic percentage concentration of silicon in a layer of the stacked structure adjacent to the work function layer; and
forming a gate electrode layer on the gate barrier layer structure.

2. The method according to claim 1 , wherein the dielectric barrier layer structure includes:
a first dielectric barrier layer doped with silicon on the gate dielectric layer, and
a second dielectric barrier layer on the first dielectric barrier layer.

3. The method according to claim 2 , wherein:
a thickness of the first dielectric barrier layer is in a range of approximately from 20 Å to 40 Å.

4. The method according to claim 2 , wherein:
the first dielectric barrier layer is made of a material including silicon-doped titanium nitride.

5. The method according to claim 2 , wherein:
an atomic percentage concentration of silicon in the first dielectric barrier layer is in a range of approximately 5%-15%.

6. The method according to claim 4 , wherein:
the first dielectric barrier layer structure is formed by an atomic layer deposition process and the first silicon source gas includes trisilylamine;
the atomic layer deposition process includes a reaction gas of the first silicon source gas and a titanium source gas, wherein the first silicon source gas has a flow rate in a range of approximately from 50 standard milliliters/minute to 150 standard milliliters/minute, and the titanium source gas includes TiCl 4 with a flow rate in a range of approximately from 100 standard milliliters/minute to 300 standard milliliters/minute;
the atomic layer deposition process further includes a deposition temperature in a range of approximately from 200° C. to 350° C. and a pressure of the reaction chamber in a range of approximately from 2 Torr to 10 Torr.

7. The method according to claim 2 , wherein:
a thickness of the second dielectric barrier layer is in a range of approximately from 10 Å to 20 Å.

8. The method according to claim 2 , wherein:
the second dielectric barrier layer is made of a material including titanium nitride; and
the second dielectric barrier layer is formed by an atomic layer deposition process.

9. The method according to claim 1 , wherein the gate barrier layer structure includes:
a first gate barrier layer on the work function layer, and
a second gate barrier layer on the first gate barrier layer,
wherein the second gate barrier layer is doped with silicon.

10. The method according to claim 9 , wherein:
a thickness of the first gate barrier layer is in a range of approximately from 10 Å to 20 Å.

11. The method according to claim 9 , wherein:
the first gate barrier layer is made of a material including titanium nitride; and
the first gate barrier layer is formed by an atomic layer deposition process.

12. The method according to claim 9 , wherein:
a thickness of the second gate barrier layer is in a range of approximately from 20 Å to 40 Å.

13. The method according to claim 9 , wherein:
the second gate barrier layer is made of a material including silicon-doped titanium nitride.

14. The method according to claim 9 , wherein:
an atomic percentage concentration of silicon in the second gate barrier layer is in a range of approximately 5%-15%.

15. The method according to claim 13 , wherein:
the second gate barrier layer is formed by an atomic layer deposition process, and the second silicon source gas includes trisilylamine;
the atomic layer deposition process includes a reaction gas of the second silicon gas and a titanium source gas, wherein the flow rate of the second silicon source gas is in a range of approximately from 50 standard milliliters/minute to 150 standard milliliters/minute, and the titanium source gas includes TiCl 4 with a flow rate in a range of approximately from 100 standard milliliters/minute to 300 standard milliliters/minute; and
the atomic layer deposition process further includes a deposition temperature in a range of approximately from 200° C. to 350° C. and a pressure of the reaction chamber in a range of approximately from 2 Torr to 10 Torr.

16. The method according to claim 1 , wherein:
each of the first and second silicon source gases includes trisilylamine or a combination of trisilylamine and silane.

17. The method according to claim 2 , wherein:
the average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than the average atomic percentage concentration of silicon in the first dielectric barrier layer.

18. The method according to claim 9 , wherein:
the gate barrier layer structure have stacked structures, and
an average atomic percentage concentration of silicon in the gate barrier layer structure is smaller than an average atomic percentage concentration of silicon in the second gate barrier layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Deng Hao

Classifications

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title