Integrated passive devices on chip

Patent metadata

Field	Value
Publication number	US-10483249-B2
Application number	US-201516060658-A
Country	US
Kind code	B2
Filing date	Dec 26, 2015
Priority date	Dec 26, 2015
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.

First claim

What is claimed is:

1. A device comprising:
a semiconductor die;
a semiconductor die package, a first side of the package being coupled with the semiconductor die; and
one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors and a plurality of capacitors, and wherein a first separate die includes a first set of passive components on a first side of the first separate die and a second, different set of passive components on a second, opposite side of the first separate die.

2. The device of claim 1 , wherein the one or more separate dies further include one or more high voltage transistors.

3. The device of claim 2 , wherein the one or more high voltage transistors includes one or more GaN (gallium nitride) transistors.

4. The device of claim 1 , wherein the one or more separate dies are coupled with a second, opposite side of the package and are electrically connected with the semiconductor die through the package.

5. The device of claim 4 , further comprising a motherboard, the one or more separate dies being coupled between the package and the motherboard, the package being connected to the motherboard by solder balls.

6. The device of claim 1 , further comprising an interposer between the semiconductor die and the semiconductor die package, wherein the one or more separate dies are embedded inside the interposer.

7. The device of claim 1 , wherein the first side of the first separate die includes a set of a first type of capacitor and a set of inductors, and the second side of the first separate die includes a set of a second type of capacitor.

8. The device of claim 7 , wherein the first type of capacitor is a two dimensional planar capacitor.

9. The device of claim 7 , wherein the first separate die includes a porous material, and wherein the second type of capacitor includes a three dimensional capacitor formed in the pores of the porous material.

10. The device of claim 9 , wherein the three dimensional capacitor is a MIM (metal-insulator-metal) capacitor.

11. The device of claim 1 , wherein the semiconductor die is system on chip (SoC).

12. A method comprising:
fabricating one or more separate dies, the one or more separate dies including a plurality of passive components;
coupling a first side of a semiconductor die package with a semiconductor die; and
coupling the one or more separate dies with the semiconductor die package to provide passive components for operation of the semiconductor die;
wherein the plurality of passive components includes one or more inductors and a plurality of capacitors; and
wherein fabricating the one or more separate dies includes fabricating a first separate die with a first set of passive components on a first side of the first separate die and a second, different set of passive components on a second, opposite side of the first separate die.

13. The method of claim 12 , wherein the one or more separate dies further include one or more high voltage transistors.

14. The method of claim 12 , wherein coupling the one or more separate dies with the semiconductor die package includes coupling the one or more separate dies with a second, opposite side of the package, and electrically connected the one or more separate dies with the semiconductor die through the package.

15. The method of claim 12 , wherein the first side of the first separate die includes a set of a first type of capacitor and a set of inductors, and the second side of the first separate die includes a set of a second type of capacitor.

16. The method of claim 15 , wherein the first type of capacitor is a two dimensional planar capacitor.

17. The method of claim 15 , wherein fabricating the one or more separate dies includes fabricating a porous material on the second side of the first separate die and fabricating a three dimensional capacitor in the pores of the porous material.

18. The method of claim 17 , wherein fabricating the three dimensional capacitor includes fabricating one or more MIM (metal-insulator-metal) capacitors.

19. A system comprising:
a system on chip;
a semiconductor die package, a first side of the package being coupled with the system on chip;
one or more separate dies to provide a plurality of passive components for operation of the system on chip, a first side of each of the one or more separate dies being coupled to a second, opposite side of semiconductor die package;
a mother board, the motherboard being coupled with the second side of the semiconductor die package and a second, opposite side of each of the one or more separate dies, the one or more separate dies being between the semiconductor die package and the motherboard;
wherein the plurality of passive components includes a plurality of inductors, wherein the one or more separate dies further include one or more high voltage transistors.

20. The system of claim 19 , the plurality of passive components further includes a plurality of capacitors.

21. A device comprising:
a semiconductor die;
a semiconductor die package, a first side of the package being coupled with the semiconductor die; and
one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the one or more separate dies further include one or more high voltage transistors, and wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors.

22. The device of claim 21 , wherein the one or more high voltage transistors includes one or more GaN (gallium nitride) transistors.

23. A device comprising:
a semiconductor die;
a semiconductor die package, a first side of the package being coupled with the semiconductor die;
one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors; and
an interposer between the semiconductor die and the semiconductor die package, wherein the one or more separate dies are embedded inside the interposer.

24. A method comprising:
fabricating one or more separate dies, the one or more separate dies including a plurality of passive components;
coupling a first side of a semiconductor die package with a semiconductor die; and
coupling the one or more separate dies with the semiconductor die package to provide passive components for operation of the semiconductor die, wherein the one or more separate dies further include one or more high voltage transistors, and wherein the plurality of passive components includes one or more inductors.

Assignees

• Intel Corp

Inventors

• Gardner Donald S
• Burton Edward A
• Schrom Gerhard
• Mosley Larry E

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title