Wafer level chip scale filter packaging using semiconductor wafers with through wafer vias

Patent metadata

Field	Value
Publication number	US-10483248-B2
Application number	US-201815912924-A
Country	US
Kind code	B2
Filing date	Mar 6, 2018
Priority date	Mar 23, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon. The RF filter is disposed within the cavity defined in the semiconductor substrate.

First claim

What is claimed is:

1. An electronics package comprising:
a semiconductor substrate having one or more passive devices formed on the semiconductor substrate and a cavity defined in a first surface of the semiconductor substrate; and
a piezoelectric substrate bonded to the semiconductor substrate and having a microelectromechanical device formed on the piezoelectric substrate, the microelectromechanical device disposed within the cavity defined in the semiconductor substrate.

2. The package of claim 1 wherein the one or more passive devices are disposed within the cavity.

3. The package of claim 1 wherein the microelectromechanical device is one of a surface acoustic wave filter and a bulk acoustic wave filter.

4. The package of claim 1 wherein the semiconductor substrate includes a plurality of bond pads formed on a second surface of the semiconductor substrate.

5. The package of claim 4 wherein the piezoelectric substrate includes one or more bond pads electrically connected to one or more of the plurality of bond pads formed on the second surface of the semiconductor substrate.

6. The package of claim 5 wherein the one or more bond pads of the piezoelectric substrate are electrically connected to the one or more of the plurality of bond pads formed on the second surface of the semiconductor substrate by through-wafer vias passing through the semiconductor substrate.

7. The package of claim 1 configured as a flip-chip package.

8. The package of claim 1 wherein the one or more passive devices are disposed on a second surface of the semiconductor substrate opposite the first surface.

9. The package of claim 8 wherein the semiconductor substrate includes a plurality of bond pads formed on the second surface thereof.

10. The package of claim 1 further including a seal ring hermetically sealing the cavity.

11. The package of claim 1 wherein side walls and an upper wall of the cavity are coated with a metal film.

12. The package of claim 1 wherein the semiconductor substrate is free of microelectromechanical system (MEMS) devices.

13. The package of claim 1 further comprising a passivation film disposed on the semiconductor substrate and one or more passive devices.

14. A module for an electronic device including an electronics package, the electronics package comprising:
a semiconductor substrate having one or more passive devices formed on the semiconductor substrate and a cavity defined in a first surface of the semiconductor substrate; and
a piezoelectric substrate bonded to the semiconductor substrate and having a microelectromechanical device formed on the piezoelectric substrate, the microelectromechanical device disposed within the cavity defined in the semiconductor substrate.

15. The module of claim 14 wherein the one or more passive devices are disposed within the cavity.

16. The module of claim 14 wherein the microelectromechanical device is one of a surface acoustic wave filter and a bulk acoustic wave filter.

17. The module of claim 14 wherein the one or more passive devices are disposed on a second surface of the semiconductor substrate opposite the first surface.

18. The module of claim 14 wherein side walls and an upper wall of the cavity are coated with a metal film.

19. An electronic device including a module for an electronic device, the module including an electronics package, the electronics package comprising:
a semiconductor substrate having one or more passive devices formed on the semiconductor substrate and a cavity defined in a first surface of the semiconductor substrate; and
a piezoelectric substrate bonded to the semiconductor substrate and having a microelectromechanical device formed on the piezoelectric substrate, the microelectromechanical device disposed within the cavity defined in the semiconductor substrate.

20. The electronic device of claim 19 wherein the one or more passive devices are disposed within the cavity.

21. The electronic device of claim 19 wherein the microelectromechanical device is one of a surface acoustic wave filter and a bulk acoustic wave filter.

22. The electronic device of claim 19 wherein the one or more passive devices are disposed on a second surface of the semiconductor substrate opposite the first surface.

Assignees

• Skyworks Solutions Inc

Inventors

• Yota Jiro
• Shen Hong
• Ramanathan Viswanathan

Classifications

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H03H9/1064

  for surface acoustic wave [SAW] devices · CPC title

• H03H3/02

  for the manufacture of piezoelectric or electrostrictive resonators or networks (H03H3/08 takes precedence) · CPC title