Method for fabricating bump structures on chips with panel type process

Patent metadata

Field	Value
Publication number	US-10483232-B2
Application number	US-201715683944-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Aug 23, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.

First claim

What is claimed is:

1. A method for fabricating a bump structure on a chip with panel type process, comprising in sequential order:
providing an integrated carrier and a plurality of semiconductor chips, which has an active side and a reverse side relative to the active side, the active side of each semiconductor chip has a plurality of metal electrode pads and an insulated protecting layer, which is exposed out of the metal electrode pads;
fixing the reverse side of each semiconductor chip on the integrated carrier;
executing an electroless plating process to form an under bump metallurgy (UBM) structure on the metal electrode pad of each semiconductor chip, wherein the coverage range of the UBM structure is equal to the coverage range of the metal electrode pad;
forming a dielectric layer to cover the integrated carrier, the semiconductor chips and the UBM structure;
forming a plurality of via holes through the dielectric layer and are exposed out of the UBM structure by laser drill or lithography including exposure and development processes; and forming a plurality of metal bumps in the corresponding via hole of the dielectric layer, respectively;
wherein the electrode pad is an aluminum metal electrode pad, and the electroless plating process includes an electroless nickel plating process, a first electroless gold plating process, an electroless palladium plating process and a second electroless gold plating process that is forming a nickel metal layer on the aluminum metal electrode pad, forming a first gold metal layer on the nickel metal layer, forming a palladium metal layer on the first gold metal layer and forming a second gold metal layer on the palladium metal layer; and
wherein the order of arrangement from below is respectively the aluminum metal electrode pad, the nickel metal layer, the first gold metal layer, the palladium metal layer, the second gold metal layer and the metal bump.

2. The method defined in claim 1 , wherein the electrode pad is a copper metal electrode pad, and the electroless plating process includes an electroless copper plating process that is forming a copper metal layer on the cooper metal electrode pad.

3. The method defined in claim 2 , wherein the order of arrangement from below is respectively the copper metal electrode pad, the copper metal layer and the metal bump.

4. The method defined in claim 1 , wherein the electrode pad is an aluminum metal electrode pad, and the electroless plating process includes an electroless copper plating process that is forming a copper metal layer on the aluminum metal electrode pad.

5. The method defined in claim 4 , wherein the order of arrangement from below is respectively the aluminum metal electrode pad, the copper metal layer and the metal bump.

6. The method defined in claim 1 , wherein the electrode pad is an aluminum metal electrode pad, and the electroless plating process includes an electroless nickel plating process and an electroless copper plating process that is forming a nickel metal layer on the aluminum metal electrode pad and forming a copper metal layer on the nickel metal layer.

7. The method defined in claim 6 , wherein the order of arrangement from below is respectively the aluminum metal electrode pad, the nickel metal layer, the copper metal layer and the metal bump.

8. The method defined in claim 1 , wherein the electrode pad is an aluminum metal electrode pad, and the electroless plating process includes a first electroless gold plating process, an electroless palladium plating process and a second electroless gold plating process that is forming a first gold metal layer on the aluminum metal electrode pad, forming a palladium metal layer on the first gold metal layer and forming a second gold metal layer on the palladium metal layer.

9. The method defined in claim 8 , wherein the order of arrangement from below is respectively the aluminum metal electrode pad, the first gold metal layer, the palladium metal layer, the second gold metal layer and the metal bump.

10. The method defined in claim 1 , further comprising:
forming a patterned dry film on the dielectric layer, wherein the patterned dry film includes a plurality of dry film openings to expose the via holes, the UBM structure and apportion of the dielectric layer.

11. The method defined in claim 10 , wherein the step of forming the metal bump includes forming the metal bumps in the via holes and the dry film openings.

12. The method defined in claim 1 , further comprising:
forming a redistribution layer on the metal bumps, wherein the redistribution layer is electrically connected to the metal electrode pads of the semiconductor chips through the metal bumps and the UBM structure.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping
• Hsu Che-Wei
• Kuo Tung-Yao

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title