Dual demarcation voltage sensing before writes

Patent metadata

Field	Value
Publication number	US-10482960-B2
Application number	US-201615046339-A
Country	US
Kind code	B2
Filing date	Feb 17, 2016
Priority date	Feb 17, 2016
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells; and
circuitry configured to:
apply a set demarcation bias voltage (Vdms) to a plurality of cells and detect the presence or absence of a resulting transient snapback current;
after applying the set demarcation bias voltage (Vdms) to the plurality of cells, receive at least a portion of data comprising set bits and reset bits;
identify an array location to write data comprising set bits and reset bits;
map the set bits and the reset bits of the data to corresponding cells of the array location;
apply a reset demarcation bias voltage (Vdmr) to reset bit-mapped cells and detect the presence or absence of a resulting transient snapback current, wherein Vdmr has a higher voltage than Vdms;
apply a set pulse to set bit-mapped cells in which the transient snapback current is absent; and
apply a reset pulse to reset bit-mapped cells in which the transient snapback current is present.

2. The device of claim 1 , wherein the circuitry is further configured to:
after applying the set pulse to set bit-mapped cells in which the transient snapback current is absent, inhibit further application of the set pulse to snapback-positive set bit-mapped memory cells; and
after applying the reset pulse to reset bit-mapped cells in which the transient snapback current is present, inhibit further application of the reset pulse to snapback-negative reset bit-mapped memory cells.

3. The device of claim 1 , wherein the circuitry is further configured to receive the portion of the data after application of Vdms and before application of Vdmr.

4. The device of claim 3 , wherein the circuitry is further configured to apply the Vdms prior to determining the set bit-mapped cells.

5. The device of claim 3 , wherein the circuitry is further configured to apply the Vdms prior to determining the reset bit-mapped cells.

6. The device of claim 3 , wherein the circuitry is further configured to apply the Vdmr to the reset bit-mapped cells.

7. The device of claim 3 , wherein the circuitry is further configured to apply the Vdmr to only the reset bit-mapped cells.

8. The device of claim 1 , wherein the circuitry is further configured to apply Vdmr after receipt of the portion of the data and to apply Vdms before receipt of the portion of the data.

9. The device of claim 1 , wherein the circuitry is further configured to apply Vdms such that at least a portion of the memory cells in the array location receive Vdms.

10. The device of claim 1 , wherein the array of memory cells comprises one or more of: byte addressable memory, memory devices that use chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level PCM, a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque (STT)-MRAM.

11. A method for controlling a memory, the method comprising:
applying set demarcation bias voltages (Vdms) to a plurality of memory cells and detecting the presence or absence of a resulting transient snapback current;
after applying the set demarcation bias voltage (Vdms) to the plurality of memory cells, receiving at least a portion of data comprising set bits and reset bits;
identifying an array location to write data comprising set bits and reset bits;
mapping the set bits and the reset bits of the data to corresponding cells of the array location;
applying reset demarcation bias voltages (Vdmr) to reset bit-mapped memory cells and detecting the presence or absence of a resulting transient snapback current, wherein Vdmr has a higher voltage than Vdms;
applying set pulses to set bit-mapped memory cells in which the transient snapback current is absent; and
applying reset pulses to reset bit-mapped memory cells in which the transient snapback current is present.

12. The method of claim 11 , further comprising:
after applying the set pulses to the set bit-mapped memory cells in which the transient snapback current is absent, inhibiting further application of the set pulses to snapback-positive set bit-mapped memory cells; and
after applying the reset pulses to the reset bit-mapped memory cells in which snapback current is present, inhibiting further application of the reset pulses to snapback-negative reset bit-mapped memory cells.

13. The method of claim 11 , further comprising applying Vdmr after receipt of the data and to apply Vdms before receipt of at least a portion of the data.

14. The method of claim 11 , wherein the memory cell array comprises one or more of: byte addressable memory, memory devices that use chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level PCM, a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque (STT)-MRAM.

Assignees

• Intel Corp

Inventors

• Chu Daniel
• Pangal Kiran
• Taub Mase
• Guliani Sandeep
• Zeng Raymond

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title