Resistive RAM memory cell

Patent metadata

Field	Value
Publication number	US-10482957-B2
Application number	US-201815978003-A
Country	US
Kind code	B2
Filing date	May 11, 2018
Priority date	May 12, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.

First claim

The invention claimed is:

1. A memory cell comprising:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in a substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the memory element rests at least partially on a top surface of the gate of the selection transistor.

2. The memory cell according to claim 1 , in which the memory element includes L-shaped constituent layers having substantially vertical portions that extend along the sidewall of the gate and substantially horizontal portions that extend at least partially on the conductive zone of selection transistor.

3. The memory cell according to claim 2 , in which the constituent layers of the memory element include a conductive contact spacer that extends on the L-shaped constituent layer and does not extend above a height of the gate.

4. The memory cell according to claim 1 , in which the memory element is of OxRAM type.

5. The memory cell according to claim 1 , in which the memory element and the transistor are formed on a silicon-on-insulator substrate.

6. The memory cell according to claim 1 , in which the memory element comprises, on said conductive zone, a layer of a metal oxide chosen from the group consisting of HfO 2 and Ta 2 O 5 and a layer of an oxidizable metal chosen from the group comprising consisting of titanium and hafnium.

7. The memory cell according to claim 1 , in which said conductive zone is made of titanium nitride.

8. A memory, comprising:
a substrate layer; and
first and second memory cells each including:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side, wherein in each of the first and second memory cells, the memory element of the memory cell rests at least partially on a top surface of the gate of the selection transistor of the memory cell.

9. The memory according to claim 8 , wherein the substrate layer is part of a silicon-on-insulator substrate.

10. The memory according to claim 9 , comprising insulation between the conductive zone of the first memory cell and the conductive zone of the second memory cell.

11. The memory according to claim 8 , wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is spaced apart from, and electrically connected to, the first contact.

12. The memory according to claim 8 , wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is contiguous with the first contact.

13. The memory according to claim 8 , wherein in each of the first and second memory cells, the memory element includes L-shaped constituent layers having substantially vertical portions that extend along the sidewall of the gate and substantially horizontal portions that extend at least partially on the conductive zone of the selection transistor of the memory cell.

14. The memory according to claim 13 , wherein in each of the first and second memory cells, the constituent layers of the memory element include a conductive contact spacer that extends on the L-shaped constituent layer and does not extend above a height of the gate of the selection transistor of the memory cell.

15. The memory according to claim 8 , wherein in each of the first and second memory cells, the memory element comprises, on said conductive zone, a layer of a metal oxide chosen from the group consisting of HfO 2 and Ta 2 O 5 and a layer of an oxidizable metal chosen from the group consisting of titanium and hafnium.

16. A memory, comprising:
a silicon on insulator substrate that includes a semiconductor layer on a buried insulating layer;
first and second memory cells each including:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side; and

an insulating region extending between the conductive zone of the first memory cell and the conductive zone of the second memory cell, the insulating region including a portion of the buried insulating layer.

17. The memory according to claim 16 , wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is spaced apart from, and electrically connected to, the first contact.

18. The memory according to claim 16 , wherein the memory element of the first memory cell includes a conductive first contact and the memory element of the second memory cell includes a conductive second contact that is contiguous with the first contact.

Assignees

• St Microelectronics Rousset

Inventors

• Boivin Philippe
• Jeannot Simon
• Weber Olivier

Classifications

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/003 Primary

  Cell access · CPC title