Thermal resistance analysis model and semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-10482199-B2
Application number	US-201715813283-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	May 18, 2015
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A thermal resistance analysis model of a semiconductor integrated circuit comprising a die and a semiconductor chip disposed on the die, the die constituting a bottom inner node BI, the semiconductor chip including a local heat-generating portion constituting a junction node JN, the semiconductor chip constituting an additional plate node PN, a first thermal resistance θJP between the junction node JN and the additional plate node PN; and a second thermal resistance θPBI between the additional plate node PN and the bottom inner node BI, wherein the semiconductor integrated circuit is expressed by a multi-thermal resistance network. Disclosed herein are a thermal resistance analysis model with satisfactory precision as a thermal resistance analysis model of locally heat-generating semiconductor integrated circuits; and a semiconductor integrated circuit to which such a thermal resistance analysis model is applied.

First claim

What is claimed is:

1. A thermal resistance analysis model of a semiconductor integrated circuit comprising a die on which a semiconductor chip is disposed, the thermal resistance analysis model comprising:
a bottom inner node at the die;
a local heat-generating portion constituting a junction node and an additional plate node at the semiconductor chip;
a first thermal resistance between the junction node and the additional plate node; and
a second thermal resistance between the additional plate node and the bottom inner node, wherein
the semiconductor integrated circuit is modeled and analyzed using a multi-thermal resistance network.

2. The thermal resistance analysis model according to claim 1 , wherein
the additional plate node is disposed at a substantially center portion of the semiconductor chip in a planar view.

3. The thermal resistance analysis model according to claim 1 , wherein the semiconductor integrated circuit further comprises:
a top inner node;
a top outer node;
a side node;
a lead node; and
a bottom outer node.

4. The thermal resistance analysis model according to claim 3 , wherein
the lead node further comprising a lead foot node and a lead side node.

5. The thermal resistance analysis model according to claim 3 , wherein:
the bottom inner node and the bottom outer node correspond respectively to an inside and an outside of a mounting substrate, the semiconductor chip being mounted on the mounting substrate, in the semiconductor integrated circuit;
the top inner node and the top outer node correspond respectively to an inside and an outside of an upper surface case, the semiconductor chip is disposed in the upper surface case, in the semiconductor integrated circuit;
the junction node corresponds to a junction portion, the junction portion becoming a heat source of the semiconductor chip, in the semiconductor integrated circuit; and
the side node and the lead node correspond respectively to a side portion of the upper surface case and a disposing portion of a lead terminal, the semiconductor chip is disposed in the upper surface case, in the semiconductor integrated circuit.

6. The thermal resistance analysis model according to claim 1 , further comprising:
a substrate disposed in the semiconductor integrated circuit, the substrate configured to mount the die.

7. The thermal resistance analysis model according to claim 6 , wherein the substrate comprises
an insulating substrate, and
a first electrode layer disposed on the insulating substrate, wherein
the semiconductor chip is mounted on the first electrode layer via the die.

8. The thermal resistance analysis model according to claim 6 , wherein the substrate comprises
an insulating substrate,
a first electrode layer disposed on the insulating substrate, and
a second electrode layer disposed on a back side surface opposite to the first electrode layer of the insulating substrate, wherein
the semiconductor chip is mounted on the first electrode layer via the die.

9. The thermal resistance analysis model according to claim 6 , wherein the substrate comprises
an insulating substrate,
a first electrode layer disposed on the insulating substrate,
a second electrode layer disposed on a back side surface opposite to the first electrode layer of the insulating substrate,
a first plane electrode layer embedded in an inside of the insulating substrate, and
a second plane electrode layer embedded in an inside of the insulating substrate between the first plane electrode layer and the second electrode layer, wherein
the semiconductor chip is mounted on the first electrode layer via the die.

10. The thermal resistance analysis model according to claim 1 , wherein
the semiconductor chip comprises a plurality of heat sources, and
the local heat-generating portion comprises one heat source, the plurality of heat sources being merged into the one heat source.

11. The thermal resistance analysis model according to claim 1 , wherein
the semiconductor chip comprised heat sources of a plurality of channels, and
the local heat-generating portion comprises a heat source of arbitrary one channel in the plurality of channels.

12. The thermal resistance analysis model according to claim 11 , wherein
the heat sources of the plurality of channels comprises a junction portion of a plurality of power transistors disposed in parallel to each other.

13. A thermal resistance analysis model of a semiconductor integrated circuit comprising a die on which a semiconductor chip is disposed, the thermal resistance analysis model comprising:
a bottom inner node at the die;
a first local heat-generating portion constituting a first junction node, a second local heat-generating portion constituting a second junction node and an additional plate node at the semiconductor chip, wherein the second local heat-generating portion separated from the first local heat-generating portion;
a first thermal resistance between the first junction node and the additional plate node;
a second thermal resistance between the additional plate node and the bottom inner node;
a third thermal resistance between the additional plate node and the second junction node; and
a fourth thermal resistance between the first junction node and the second junction node, wherein
the semiconductor integrated circuit is modeled and analyzed using a multi-thermal resistance network.

14. The thermal resistance analysis model according to claim 13 , wherein
the additional plate node is disposed at a substantially center portion of the semiconductor chip in a planar view.

15. The thermal resistance analysis model according to claim 13 , wherein the semiconductor integrated circuit further comprising:
a top inner node;
a top outer node;
a side node;
a lead node; and
a bottom outer node.

16. The thermal resistance analysis model according to claim 15 , wherein
the lead node further comprising a lead foot node and a lead side node.

17. The thermal resistance analysis model according to claim 15 , wherein
the bottom inner node and the bottom outer node respectively correspond respectively to an inside and an outside of a mounting substrate, the semiconductor chip being mounted on the mounting substrate, in the semiconductor integrated circuit;
the top inner node and the top outer node correspond respectively to an inside and an outside of an upper surface case, the semiconductor chip is disposed in the upper surface case, in the semiconductor integrated circuit;
the first junction node and the second junction node correspond respectively to two junction portions, the two junction portions respectively becoming heat sources of the semiconductor chip, in the semiconductor integrated circuit; and
the side node and the lead node correspond respectively to a side portion of the upper surface case and a disposing portion of a lead terminal, the semiconductor chip is disposed in the upper surface case, in the semiconductor integrated circuit.

18. The thermal resistance analysis model according to claim 15 , wherein
the semiconductor chip comprises an integrated circuit for system power supply.

19. The thermal resistance analysis model according to claim 18 , wherein
the first local heat-generating portion and the second local heat-generating portion comprise heat generation profiles different from each other.

20. A semiconductor integrated circuit to which the thermal resistance analysis model according to claim 1 is applied.

Assignees

• Rohm Co Ltd

Inventors

• Yasutake Ippei

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F30/22 Primary

  using Petri net models · CPC title

• G06F30/00 Primary

  Computer-aided design [CAD] · CPC title