Equalizer circuit, receiver circuit, and integrated circuit device

Patent metadata

Field	Value
Publication number	US-10476710-B2
Application number	US-201816209616-A
Country	US
Kind code	B2
Filing date	Dec 4, 2018
Priority date	Jun 24, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.

First claim

What is claimed is:

1. An equalizer circuit comprising:
a first adder circuit configured to add an input signal and including an addition terminal and a subtraction terminal;
a comparator circuit configured to compare an output signal of the first adder circuit;
a latch circuit configured to latch data output from the comparator circuit;
a first digital/analog converter circuit configured to output a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value;
a second digital/analog converter circuit configured to output a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and
a switch circuit configured to switch a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.

2. The equalizer circuit according to claim 1 , wherein
the first digital/analog converter circuit is configured to output a signal corresponding to a signal in the case of the equalizing coefficient being zero, when the equalizing coefficient is a negative value, and
the second digital/analog converter circuit is configured to output a signal corresponding to a signal in the case of the equalizing coefficient being zero, when the equalizing coefficient is a positive value.

3. The equalizer circuit according to claim 1 , wherein
the first signal and second signal are a first current signal and a second current signal,
the first digital/analog converter circuit and the second digital/analog converter circuit are a first current DAC and a second current DAC.

4. The equalizer circuit according to claim 1 , wherein
the equalizer circuit includes n inter-symbol interference removal units configured to remove inter-symbol interference due to past n data, where n is an integer of 2 or more,
each of the inter-symbol interference removal units includes a corresponding latch circuit, a corresponding first digital/analog converter circuit, a corresponding second digital/analog converter circuit, and a corresponding switch circuit, and
the latch circuits included in the n inter-symbol interference removal units are connected in series and constituted as a shift register for storing data of symbols up to n-th previous data.

5. A receiver circuit comprising:
the equalizer circuit according to claim 1 ;
a demultiplexer configured to receive data output from the equalizer circuit, perform a serial/parallel conversion, and output received parallel data accompanied with a receive clock; and
a clock generation circuit configured to generate a data sampling clock used in the equalizer circuit based on an output signal of the demultiplexer.

6. An integrated circuit device comprising:
the receiver circuit according to claim 5 ;
an internal circuit configured to receive the received parallel data and the receive clock from the receiver circuit, and perform processing; and
a transmitter circuit configured to receive transmit parallel data and a transmit clock from the internal circuit, perform a parallel/serial conversion, and output a serial converted transmit signal.

7. An equalizer circuit comprising:
a first adder circuit configured to add an input signal and including an addition terminal and a subtraction terminal;
a comparator circuit configured to compare an output signal of the first adder circuit;
a latch circuit configured to latch data output from the comparator circuit;
a digital/analog converter circuit configured to output a third signal corresponding to an absolute value of an equalizing coefficient; and
a switch circuit configured to switch a connection between an output terminal of the digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit and sign information of the equalizing coefficient.

8. The equalizer circuit according to claim 7 , wherein
the switch circuit includes:
a first switch circuit configured to switch a connection between the output terminal of the digital/analog converter circuit and output terminals of the first switch circuit, based on the data latched in the latch circuit; and
a second switch circuit configured to switch a connection between the output terminals of the first switch circuit, and the set of the addition terminal and the subtraction terminal, based on the sign information of the equalizing coefficient.

9. The equalizer circuit according to claim 8 , wherein
the third signal is a third current signal, and
the digital/analog converter circuit is a current DAC.

10. The equalizer circuit according to claim 8 , wherein
the equalizer circuit includes n inter-symbol interference removal units configured to remove inter-symbol interference due to past n data, where n is an integer of 2 or more,
each of the inter-symbol interference removal units includes a corresponding latch circuit, a corresponding digital/analog converter circuit, and a corresponding switch circuit, and
the latch circuits included in the n inter-symbol interference removal units are connected in series and constituted as a shift register for storing data of symbols up to n-th previous data.

11. A receiver circuit comprising:
the equalizer circuit according to claim 8 ;
a demultiplexer configured to receive data output from the equalizer circuit, perform a serial/parallel conversion, and output received parallel data accompanied with a receive clock; and
a clock generation circuit configured to generate a data sampling clock used in the equalizer circuit base on an output signal of the demultiplexer.

12. An integrated circuit device comprising:
the receiver circuit according to claim 11 ;
an internal circuit configured to receive the received parallel data and the receive clock from the receiver circuit, and perform processing; and
a transmitter circuit configured to receive transmit parallel data and a transmit clock from the internal circuit, perform a parallel/serial conversion, and output a serial converted transmit signal.

13. An equalizer circuit comprising:
a first adder circuit configured to add an input signal and including an addition terminal and a subtraction terminal;
a comparator circuit configured to compare an output signal of the first adder circuit;
a latch circuit configured to latch a first value based on data output from the comparator circuit;
a digital/analog converter circuit configured to output a fourth signal corresponding to an absolute value of an equalizing coefficient; and
a switch circuit configured to switch a connection between an output terminal of the digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, wherein
the first value is a value obtained by multiplying the data output from the comparator circuit and sign information of the equalizing coefficient.

14. The equalizer circuit according to claim 13 , wherein
the equalizer circuit includes n inter-symbol interference removal units configured to remove inter-symbol interference due to past n data, where n is an integer of 2 or more,
each of the inter-symbol interference removal units includes a corresponding latch circuit, a corresponding digital/analog converter circuit, and a corresponding switch circuit, and
the latch circuits included in the n inter-symbol interference removal units are connected in series and constitu

Assignees

• Socionext Inc

Inventors

• Kudo Masahiro
• Suzuki Daisuke

Classifications

• H04L2025/0349

  as a feedback filter · CPC title

• H04L7/0058

  detection of error based on equalizer tap values · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/03681

  Control of adaptation · CPC title

• H04B3/06 Primary

  by the transmitted signal · CPC title