Class-F power amplifier matching network

Patent metadata

Field	Value
Publication number	US-10476451-B2
Application number	US-201815872740-A
Country	US
Kind code	B2
Filing date	Jan 16, 2018
Priority date	Jan 16, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

First claim

What is claimed is:

1. A power amplifier comprising:
a first switch comprising a first drain terminal;
a second switch comprising a second drain terminal, wherein the first switch and the second switch are configured to receive differential signals representing an input signal, the input signal having a first harmonic frequency (f H1 ), a second harmonic frequency (f H2 ) and a third harmonic frequency (f H3 );
a second harmonic trap circuitry configured to be coupled to the first drain terminal and the second drain terminal, and configured to have a first impedance between the first drain terminal and a common voltage at the second harmonic frequency, and a second impedance between the first drain terminal and the common voltage at the third harmonic frequency, wherein the first impedance is smaller than the second impedance, and wherein
the second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components;
a pair of differential output terminals coupled to the first and second drain terminals; and
a common mode trap circuitry coupled between the pair of differential output terminals, wherein the common mode trap circuitry having a first circuit path in parallel with a second circuit path, wherein the first circuit path comprises inductive and capacitive components configured to short a common mode signal at the pair of differential output terminals to the common voltage at the first harmonic frequency, and the second circuit path comprises inductive and capacitive components configured to short the common mode signal at the pair of differential output terminals to the common voltage at the third harmonic frequency.

2. The power amplifier of claim 1 , wherein:
the second harmonic trap circuitry is configured to have a third impedance between the second drain terminal and the common voltage at the second harmonic frequency, and a fourth impedance between the second drain terminal and the common voltage at the third harmonic frequency, wherein the third impedance is smaller than the fourth impedance.

3. The power amplifier of claim 1 , wherein:
the second harmonic trap circuitry is configured to provide a short between the first drain terminal and the common voltage, and between the second drain terminal and the common voltage at the second harmonic frequency.

4. The power amplifier of claim 1 , wherein:
the first switch and the second switch are Si MOS transistors on a semiconductor die.

5. The power amplifier of claim 1 , wherein:
the second harmonic trap circuitry comprises a first node coupled to the first drain terminal by a first group of lumped inductive and capacitive components of the plurality of lumped inductive and capacitive components, and to the second drain terminal by a second group of lumped inductive and capacitive components of the plurality of lumped inductive and capacitive components, and wherein
the first node is coupled to the common voltage by a common mode inductor.

6. The power amplifier of claim 5 , wherein:
the first group of lumped inductive and capacitive components comprises a serial capacitor and a serial inductor.

7. The power amplifier of claim 1 , further comprising:
a pair of differential output terminals coupled to the first and second drain terminals; and
a matching network configured to be coupled between the pair of differential output terminals, the matching network having a single-ended output configured to be coupled to a load resistance, wherein the matching network is configured to match an impedance between the pair of differential output terminals and the load resistance.

8. The power amplifier of claim 7 , wherein:
the matching network comprises a first matching capacitor coupled between the single-ended output and a first differential output terminal of the pair of differential output terminals; a second matching capacitor coupled between a second differential output terminal of the pair of differential output terminals and a second node; a first matching inductor coupled between the first differential output terminal and the second node; a second matching inductor coupled between the second differential output terminal and the single-ended output; and
a ground network coupled between the common voltage and the second node, wherein the second node is connected to a terminal of a capacitor and a terminal of an inductor.

9. The power amplifier of claim 8 , wherein:
the ground network is configured to have a first ground network impedance at the first harmonic frequency, and a second ground network impedance at the third harmonic frequency different from the first ground network impedance.

10. The power amplifier of claim 7 , wherein:
the matching network comprises a transformer with a primary coil coupled between the pair of differential output terminals and a secondary coil coupled between a terminal of the load resistance and the common voltage.

11. The power amplifier of claim 7 , further comprising a voltage supply, wherein:
the first drain terminal and the second drain terminal are connected to the voltage supply, and wherein
the first switch, the second switch and the plurality of lumped inductive and capacitive components of the second harmonic trap circuitry are disposed on a first substrate, and
the voltage supply and the matching network is disposed on a second substrate.

12. The power amplifier of claim 1 , wherein:
the magnitude of the first impedance is less than 50% of the magnitude of the second impedance.

13. A power amplifier comprising:
a first switch and a second switch configured to receive differential signals representing an input signal, the input signal having a first harmonic frequency (f H1 ), a second harmonic frequency (f H2 ) and a third harmonic frequency (f H3 );
a lumped component circuit configured to be coupled between a first drain terminal of the first switch and a second drain terminal of the second switch, the lumped component circuit having inductive components sized to resonate at the second harmonic frequency and configured to short the first drain terminal and the second drain terminal to a common voltage at the second harmonic frequency;
a pair of differential output terminals coupled to the first and second drain terminals;
a matching network coupled between the pair of differential output terminals, the matching network having a single-ended output coupled to a load resistance, wherein the matching network is configured to match an impedance between the pair of differential output terminals and the load resistance, wherein:
the matching network comprises a first matching capacitor coupled between the single-ended output and a first differential output terminal of the pair of differential output terminals; a second matching capacitor coupled between a second differential output terminal of the pair of differential output terminals and a second node; a first matching inductor coupled between the first differential output terminal and the second node; a second matching inductor coupled between the second differential output terminal and the single-ended output; and
a ground network coupled between the common voltage and the second node, wherein the second node is connected to a terminal of a capacitor and a terminal of an inductor and wherein the ground network is configured to have a first ground network impedance at the first harmonic frequency, and a second ground network impedance at the third harmonic frequency different from the first ground network impedance.

14. The power amplifier of claim 13 , wherein:
the first switch and the second switch are Si MOS transistors on a

Assignees

• Mediatek Inc

Inventors

• Guo Xiaochuan
• Ko Jenwei
• Lee Wen-Chang
• Cao Changhua
• Wang Caiyi

Classifications

• H03F2203/45638

  the LC comprising one or more coils · CPC title

• H03H7/0115

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H03F2203/45631

  the LC comprising one or more capacitors, e.g. coupling capacitors · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F3/195

  in integrated circuits · CPC title