Gate arrangements in quantum dot devices

Patent metadata

Field	Value
Publication number	US-10475912-B2
Application number	US-201815900655-A
Country	US
Kind code	B2
Filing date	Feb 20, 2018
Priority date	Feb 20, 2018
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack;
a layer of gate dielectric above the quantum well stack;
a first gate metal and a second gate metal above the layer of gate dielectric; and
a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

2. The quantum dot device of claim 1 , wherein the second dielectric material includes silicon nitride.

3. The quantum dot device of claim 1 , wherein the first dielectric material includes silicon carbide.

4. The quantum dot device of claim 1 , wherein the first dielectric material includes silicon nitride.

5. The quantum dot device of claim 1 , wherein the first dielectric material is between the second dielectric material and the layer of gate dielectric.

6. The quantum dot device of claim 1 , wherein the first dielectric material is between the second dielectric material and the layer of gate dielectric.

7. The quantum dot device of claim 1 , wherein the first gate metal is in contact with the first dielectric material and the second dielectric material, and the second gate metal is in contact with the first dielectric material and the second dielectric material.

8. The quantum dot device of claim 1 , wherein the layer of gate dielectric includes silicon oxide.

9. The quantum dot device of claim 1 , wherein the quantum well stack includes a quantum well layer, and the quantum well layer includes an isotopically purified material.

10. The quantum dot device of claim 9 , wherein the isotopically purified material includes silicon.

11. The quantum dot device of claim 1 , wherein the layer of gate dielectric includes a recess, and the first gate metal is at least partially in the recess.

12. The quantum dot device of claim 1 , wherein the quantum well stack is at least partially included in a fin.

13. The quantum dot device of claim 1 , wherein the first gate metal and the second gate metal are at least partially disposed in a trench in an insulating material above the quantum well stack.

14. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum well stack, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, a layer of gate dielectric shared by at least two gates of the plurality of gates, a gate wall on the layer of gate dielectric between at least two gates, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates.

15. The quantum computing device of claim 14 , further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

16. The quantum computing device of claim 15 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

17. A quantum dot device, comprising:
a quantum well stack;
a layer of gate dielectric above the quantum well stack;
a first gate metal and a second gate metal above the layer of gate dielectric; and
a gate wall between the first gate metal and the second gate metal;
wherein the layer of gate dielectric includes a recess, and the first gate metal is at least partially in the recess.

18. The quantum dot device of claim 17 , wherein the recess has a depth between 5 Angstroms and 3 nanometers.

19. The quantum dot device of claim 17 , wherein the gate wall includes a spacer.

20. The quantum dot device of claim 17 , wherein the gate wall includes silicon nitride.

21. The quantum dot device of claim 17 , wherein the layer of gate dielectric has a thickness between 3 nanometers and 20 nanometers.

Assignees

• Intel Corp

Inventors

• Thomas Nicole K
• Pillarisetty Ravi
• Singh Kanwaljit
• George Hubert C
• Roberts Jeanette M
• Michalak David J
• Caudillo Roman
• Yoscovits Zachary R
• Lampert Lester
• Clarke James S
• Rachmady Willy

Classifications

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/518

  Electricity · mapped topic

• H01L29/778 Primary

  Electricity · mapped topic

• H01L29/7782

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic