Transistor device with high avalanche robustness

Patent metadata

Field	Value
Publication number	US-10475880-B2
Application number	US-201715685228-A
Country	US
Kind code	B2
Filing date	Aug 24, 2017
Priority date	Aug 25, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A transistor device includes drain, source and gate nodes, a plurality of drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type complementary to the first doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.

First claim

What is claimed is:

1. A transistor device, comprising:
a drain node, a source node and a gate node;
a plurality of drift and compensation cells each comprising a drift region of a first doping type and a compensation region of a second doping type complementary to the first doping type; and
a control structure connected between the drift region of each of the drift and the compensation cells and the source node,
wherein the drift region of each of the plurality of drift and compensation cells is coupled to the drain node and the compensation region of each of the plurality of drift and compensation cells is coupled to the source node,
wherein each of the plurality of drift and compensation cells, in the current flow direction of the transistor device, has a first end, a second end opposite the first end, a first intermediate position spaced apart from the first end and the second end, and a second intermediate position spaced apart from the first end and the second end,
wherein a first doping parameter of a first doping profile that represents the doping concentration of the drift region in the current flow direction monotonically increases from the second intermediate position to the second end, and
wherein a second doping parameter of a second doping profile that represents the doping concentration of the compensation region in the current flow direction monotonically increases from the first intermediate position to the first end.

2. The transistor device of claim 1 , wherein a distance between the first intermediate position and the first end is between 40% and 60% of a distance between the first end and the second end, and wherein a distance between the second intermediate position and the second end is between 40% and 60% of the distance between the first end and the second end.

3. The transistor device of claim 1 , wherein the second doping parameter comprises a peak between the first intermediate position and the second intermediate position.

4. The transistor device of claim 1 , wherein the first doping parameter comprises a peak between the first intermediate position and the second intermediate position.

5. The transistor device of claim 1 , wherein the first doping parameter comprises a peak between the first intermediate position and the first end.

6. The transistor device of claim 5 , wherein the peak is closer to the first end than to the first intermediate position.

7. The transistor device of claim 1 , wherein the second doping parameter comprises a peak between the second intermediate position and the second end.

8. The transistor device of claim 7 , wherein the peak is closer to the second end than to the second intermediate position.

9. The transistor device of claim 1 , wherein the first doping parameter represents one of: the doping concentration of the drift region; local maxima of the doping concentration of the drift region; and a dopant dose in each of a plurality of epitaxial layers formed one above the other and each comprising a section of the drift region.

10. The transistor device of claim 1 , wherein the second doping parameter represents one of: the doping concentration of the compensation region; local maxima of the doping concentration of the compensation region; and a dopant dose in each of a plurality of epitaxial layers formed one above the other and each comprising a section of the compensation region.

11. The transistor device of claim 1 , wherein the plurality of drift and compensation cells are arranged such that the drift region of a first one of the plurality of drift and compensation cells adjoins the drift region of a second one of the plurality of drift and compensation cells, and the compensation region of the first one of the plurality of drift and compensation cells adjoins the compensation region of a third one of the plurality of drift and compensation cells.

12. The transistor device of claim 1 , wherein each of the plurality of drift and compensation cells has a voltage blocking capability and wherein the voltage blocking capabilities of the plurality of drift and compensation cells are substantially equal.

13. The transistor device of claim 1 , wherein the control structure comprises a plurality of control cells, each comprising:
a source region of the first doping type connected to the source node;
a body region of the second doping type connected to the source node; and
a gate electrode dielectrically insulated from the body region by a gate dielectric.

14. The transistor device of claim 13 , wherein the body region of each of the plurality of control cells adjoins the drift region of at least one of the plurality of drift and compensation regions.

15. The transistor device of claim 13 , wherein the body region of each of the plurality of control cells adjoins the compensation region of at least one of the plurality of drift and compensation regions.

16. The transistor device of claim 1 , further comprising:
a drain region of the first doping type connected to the drain node and coupled to the drift regions of the plurality of drift and compensation cells.

17. The transistor device of claim 16 , further comprising:
a buffer region of the first doping type coupling the drain region to the drift regions of the plurality of drift and compensation cells and having a lower doping concentration than the drain region.

18. A power converter circuit comprising an inductor and an electronic switch connected in series with the inductor, wherein the electronic switch comprises the transistor device of claim 1 .

Assignees

• Infineon Technologies Austria Ag

Inventors

• Fragiacomo Giulio
• Willmeroth Armin
• Fischer Bjoern
• Mente Rene

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M7/217

  using semiconductor devices only · CPC title

• H01L29/1095

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/7802

  Electricity · mapped topic