BEOL capacitor through airgap metallization

US10475878B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10475878-B2
Application numberUS-201715856399-A
CountryUS
Kind codeB2
Filing dateDec 28, 2017
Priority dateSep 1, 2016
Publication dateNov 12, 2019
Grant dateNov 12, 2019

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Abstract

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A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode. The manufactured product has a bottom electrode, composed of a conductor, electrically connected to upward conductive prominences; a low-K layer, above and conjoined to the bottom layer and surrounding the prominences, composed of a low-K dielectric; an isolation layer, above the low-K layer and surrounding the prominences, composed of a high-K insulator material, where modulating its material and thickness controls the capacitance; and a top electrode, composed of a conductor and electrically connected to downward prominences, where the bottom and top electrodes are interconnected.

First claim

Opening claim text (preview).

What we claim is: 1. A method comprising: patterning a first array for a first electrode in a semiconductor capacitor; removing a portion of inter-layer dielectric to achieve a desired capacitor area, wherein the removing comprises removing the portion of inter-layer dielectric from between metal lines to form trenches to create an interdigitated capacitor with a plurality of first prominences each having a first height and interconnected with a plurality of second prominences each having a second height, the first height being different from the second height; depositing a dielectric for a capacitor insulator on the first prominences and on and under the second prominences, wherein variations in a material and/or thickness of the deposited dielectric determines a total capacitance of a structure formed; filling the desired capacitor area to form a second electrode on the capacitor insulator; polishing and capping the second electrode; and interconnecting the first electrode and the second electrode. 2. The method of claim 1 , wherein the first electrode comprises conductive material. 3. The method of claim 1 , wherein the patterning uses a back end-of-the-line process of record. 4. The method of claim 1 , wherein the depositing comprises at least one existing high-K materials chemical vapor deposition process. 5. The method of claim 1 , wherein the second electrode comprises conductive material. 6. The method of claim 1 , wherein the depositing uses a back end-of-the-line process of record. 7. The method of claim 1 , wherein the polishing and capping uses a back end-of-the-line process of record. 8. The method of claim 1 , wherein the interconnecting uses a back end-of-the-line process of record. 9. A computer program product embodied on a non-transitory computer-readable medium in which a computer program is stored that, when being executed by a computer, is configured to provide instructions to control or carry out the method of claim 1 . 10. The method of claim 1 , wherein the removing of the portion of inter-layer dielectric comprises forming trenches that are wider on a bottom and narrower on a top. 11. The method of claim 10 , wherein depositing the dielectric to have variations in the material and/or thickness comprises depositing the dielectric to be thicker on the bottom of a wall of the trench and thinner on the top of the wall of the trench.

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What does patent US10475878B2 cover?
A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L28/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).