Packaging substrate and method of fabricating the same
US-2017338174-A1 · Nov 23, 2017 · US
Interposer substrate and method for manufacturing the same
US10475765B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10475765-B2 |
| Application number | US-201715817450-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 20, 2017 |
| Priority date | Sep 5, 2017 |
| Publication date | Nov 12, 2019 |
| Grant date | Nov 12, 2019 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
The disclosure provides an interposer substrate and a method for manufacturing the same. The method includes forming an insulating protection layer having a phosphorus compound on a substrate body, thereby providing toughness and strength as required when the thickness of the interposer substrate becomes too thin, and preventing substrate warpage when the substrate has a shrinkage stress or structural asymmetries.
First claim
Opening claim text (preview).
What is claimed is: 1. An interposer substrate, comprising: a substrate body having a first surface and a second surface opposite to the first surface and including at least one insulating layer and a wiring portion combined with the insulating layer, the wiring portion including a wiring layer formed on the insulating layer and a plurality of conductive posts disposed in the insulating layer and electrically connected to the wiring layer; and an insulating protection layer formed on the second surface and free from being formed on the first surface of the substrate body and including a phosphorous compound, wherein the insulating protection layer has a coefficient of thermal expansion (CTE) greater than the insulating layer. 2. The interposer substrate of claim 1 , wherein the insulating layer is made of a molding compound or a primer. 3. The interposer substrate of claim 1 , wherein the phosphorous compound contains phosphorous in a range of from 10000 ppm to 30000 ppm. 4. The interposer substrate of claim 1 , wherein the substrate body and the insulating protection layer have a total thickness of less than or equal to 180 μm. 5. A method for manufacturing an interposer substrate, comprising: providing a substrate body having a first surface and a second surface opposite to the first surface and including at least one insulating layer and a wiring portion combined with the insulating layer, the wiring portion including a wiring layer formed on the insulating layer and a plurality of conductive posts disposed in the insulating layer and electrically connected to the wiring layer; and forming on the second surface and free from forming on the first surface of the substrate body an insulating protection layer including a phosphorous compound, wherein the insulating protection layer has a coefficient of thermal expansion (CTE) greater than the insulating layer. 6. The method of claim 5 , wherein the insulating layer is made a molding compound or a primer. 7. The method of claim 5 , wherein the phosphorous compound contains phosphorous in a range of from 10000 ppm to 30000 ppm. 8. The method of claim 5 , wherein the substrate body and the insulating protection layer have a total thickness of less than or equal to 180 μm.
Assignees
Inventors
Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
Encapsulations, e.g. protective coatings · CPC title
Die-attach connectors and bond wires · CPC title
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Frequently asked questions
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- What does patent US10475765B2 cover?
- The disclosure provides an interposer substrate and a method for manufacturing the same. The method includes forming an insulating protection layer having a phosphorus compound on a substrate body, thereby providing toughness and strength as required when the thickness of the interposer substrate becomes too thin, and preventing substrate warpage when the substrate has a shrinkage stress or str…
- Who is the assignee on this patent?
- Phoenix Pioneer Technology Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W72/0198. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).