Semiconductor package structure and method of making the same

Patent metadata

Field	Value
Publication number	US-10475752-B2
Application number	US-201715703022-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Jun 9, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A semiconductor package structure includes a substrate, a chip, bumps, an encapsulation layer and a thermal expansion-matching layer. The chip is located on a top surface of the substrate. The bumps electrically connect the chip and the inner connection pads of the substrate. The encapsulation layer covers the bumps, the chip and the top surface of the substrate. The thermal expansion-matching layer covers the whole top surface of the encapsulation layer, and exposes the side surfaces of the encapsulation layer. The thermal expansion coefficient of the thermal expansion-matching layer is different from that of the encapsulation layer. The side surface of the thermal expansion-matching layer is flush with that of the encapsulation layer. The thermal expansion-matching layer balances the inner stresses caused by the difference of the thermal expansion. Thus, the invention reduces the warpage problem of the formed package.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a substrate, having a top surface and a bottom surface, the substrate comprising a plurality of inner connection pads and a plurality of outer connection pads, the inner connection pads and the outer connection pads being individually disposed on the top surface and the bottom surface of the substrate;
a chip, disposed on the top surface of the substrate;
a plurality of bumps, electrically connected to the chip and the inner connection pads of the substrate;
an encapsulation layer, covering the bumps, the chip and the top surface of the substrate, the encapsulation layer having a top surface and at least one side surface; and
a thermal expansion-matching layer, covering the whole top surface of the encapsulation layer, and exposing the at least one side surface of the encapsulation layer, wherein the thermal expansion coefficient of the thermal expansion-matching layer is different from the thermal expansion coefficient of the encapsulation layer, wherein the encapsulation layer comprises a first epoxy molding compound (EMC), the thermal expansion-matching layer comprises a second EMC, the first and the second EMCs both comprise silicone, epoxy, hardener and flame retardant, and a composition ratio of the first EMC is different from a composition ratio of the second EMC.

2. The semiconductor package structure of claim 1 , wherein the first EMC is a high filler content dielectric material, which the filler content is about 70 wt. % to 90 wt. %.

3. The semiconductor package structure of claim 1 , wherein the second EMC contains about 68˜79% silicone, 10˜15% epoxy, 10˜15% hardener and 1% flame retardant.

4. The semiconductor package structure defined in claim 1 , wherein the thermal expansion-matching layer comprises epoxy or polyimide.

5. The semiconductor package structure defined in claim 1 , further comprises a plurality of solder balls, which are disposed on the bottom surface of the substrate, and electrically connected to the outer connection pads.

6. The semiconductor package structure defined in claim 1 , wherein the outer connection pads of the substrate are a plurality of lands.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping
• Hsu Che-Wei

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title