Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-10475708-B2
Application number	US-201916299395-A
Country	US
Kind code	B2
Filing date	Mar 12, 2019
Priority date	Aug 17, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a preliminary structure having a PMOS region and a NMOS region, the preliminary structure comprising:
a substrate;
two first source/drain regions formed in the substrate in the PMOS region; and
two second source/drain regions formed in the substrate in the NMOS region;

forming a first gate dielectric partially into the substrate between the first source/drain regions and a second gate dielectric partially into the substrate between the second source/drain regions;
forming a fully silicided gate electrode on the first gate dielectric, wherein forming the fully silicided gate electrode comprises forming a metal layer on the first gate dielectric but not on the second gate dielectric; and
forming a non-silicided conductive gate electrode on the second gate dielectric.

2. The method according to claim 1 , wherein forming the fully silicided gate electrode and forming the non-silicided conductive gate electrode comprise:
forming a first polysilicon portion on the first gate dielectric and a second polysilicon portion on the second gate dielectric;
implanting a n-type dopant into the second polysilicon portion by a first implantation process to form the non-silicided conductive gate electrode; and
transferring the first polysilicon portion into a fully silicided material by a silicide process to form the fully silicided gate electrode.

3. The method according to claim 2 , wherein forming the fully silicided gate electrode further comprises:
before the silicide process, thinning the first polysilicon portion by a thinning process.

4. The method according to claim 3 , wherein a thickness of the first polysilicon portion after the thinning process is less than half of a thickness of the first polysilicon portion before the thinning process.

5. The method according to claim 3 , wherein forming the fully silicided gate electrode further comprises:
in the first implantation process, implanting the n-type dopant into the first polysilicon portion.

6. The method according to claim 3 , wherein the preliminary structure further comprises:
a n-type well in the substrate in the PMOS region, wherein each of the first source/drain regions comprises a p-type doped region disposed in the n-type well; and
a p-type well in the substrate in the NMOS region, wherein each of the second source/drain regions comprises a n-type doped region disposed in the p-type well; and

the method further comprises:
implanting a p-type dopant into the p-type doped regions by a second implantation process to form heavily p-type doped regions in the p-type doped regions, respectively; and
implanting a n-type dopant into the n-type doped regions by a third implantation process to form heavily n-type doped regions in the n-type doped regions, respectively.

7. The method according to claim 6 , wherein forming the fully silicided gate electrode further comprises:
in the second implantation process, implanting the p-type dopant into the first polysilicon portion.

8. The method according to claim 6 , wherein the thinning process is conducted after the second implantation process and the third implantation process.

9. The method according to claim 6 , further comprising:
forming p-type silicide regions on the heavily p-type doped regions, respectively, and n-type silicide regions on the heavily n-type doped regions, respectively, by the silicide process.

10. The method according to claim 1 , wherein the fully silicided gate electrode is formed of nickel silicide, titanium silicide, or cobalt silicide.

Assignees

• United Microelectronics Corp

Inventors

• Li yong-liang
• Su Hao

Classifications

• H10D64/0132

  the conductor being a metallic silicide · CPC title

• H01L21/82385

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L29/4916

  Electricity · mapped topic

• H01L21/823835

  Electricity · mapped topic