Method of manufacture of a semiconductor on insulator structure

Patent metadata

Field	Value
Publication number	US-10475696-B2
Application number	US-201816001377-A
Country	US
Kind code	B2
Filing date	Jun 6, 2018
Priority date	Jul 14, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.

First claim

We claim:

1. A method of preparing a multilayer structure, the method comprising:
(a) forming a front handle silicon dioxide layer on a front handle surface of a single crystal silicon handle wafer and a back handle silicon dioxide layer on a back handle surface of a single crystal silicon handle wafer, wherein the single crystal silicon handle wafer comprises two major, generally parallel surfaces, one of which is the front handle surface of the single crystal silicon handle wafer and the other of which is the back handle surface of the single crystal silicon handle wafer, a circumferential edge joining the front handle surface and the back handle surface of the single crystal silicon handle wafer, a central plane between the front handle surface and the back handle surface of the single crystal silicon handle wafer, and a bulk region between the front and back handle surfaces of the single crystal silicon handle wafer;
(b) forming a front handle silicon nitride layer on the front handle silicon dioxide layer and a back handle silicon nitride layer on the back handle silicon dioxide layer;
(c) bonding the front handle silicon nitride layer to a donor silicon dioxide layer on a front donor surface of a single crystal silicon donor wafer to thereby form a bonded structure, wherein the single crystal silicon donor wafer comprises two major, generally parallel surfaces, one of which is the front donor surface of the single crystal silicon donor wafer and the other of which is the back donor surface of the single crystal silicon donor wafer, a circumferential edge joining the front donor surface and the back donor surface of the single crystal silicon donor wafer, a central plane between the front donor surface and the back donor surface of the single crystal silicon donor wafer, and a bulk region between the front and back donor surfaces of the single crystal silicon donor wafer, and further wherein the single crystal silicon donor wafer comprises a damage layer formed by ion implantation;
(d) removing the back handle silicon nitride layer; and
(e) removing the back handle silicon dioxide layer.

2. The method of claim 1 , wherein step (c) occurs before step (d) and before step (e).

3. The method of claim 2 , wherein the back handle silicon nitride layer is removed by plasma etching.

4. The method of claim 2 , wherein the back handle silicon dioxide layer is removed by wet etching.

5. The method of claim 1 , wherein steps (d) and (e) occur before step (c).

6. The method of claim 5 , wherein the back handle silicon nitride layer is removed by plasma etching.

7. The method of claim 5 , wherein the back handle silicon dioxide layer is removed by wet etching.

8. The method of claim 1 , wherein the front handle silicon dioxide layer is formed on the front handle surface of the single crystal silicon handle wafer and the back handle silicon dioxide layer on a back handle surface of the single crystal silicon handle wafer by thermal oxidation.

9. The method of claim 1 , wherein the front handle silicon nitride layer is formed on the front handle silicon dioxide layer and the back handle silicon nitride layer is formed on the back handle silicon dioxide layer by low pressure chemical vapor deposition.

10. The method of claim 1 , further comprising annealing the single crystal silicon handle wafer comprising the front handle silicon dioxide layer and the front handle silicon nitride layer at a temperature and duration sufficient to densify the front handle silicon dioxide layer, the front handle silicon nitride layer, or both, wherein the anneal occurs prior to bonding the front handle silicon nitride layer to the donor silicon dioxide layer on the front donor surface of a single crystal silicon donor wafer.

11. The method of claim 1 , further comprising ion milling the surface of the front handle silicon nitride layer prior to bonding the front handle silicon nitride layer to the donor silicon dioxide layer on the front donor surface of a single crystal silicon donor wafer.

12. The method of claim 1 , further comprising chemical mechanical polishing the surface of the front handle silicon nitride layer prior to bonding the front handle silicon nitride layer to the donor silicon dioxide layer on the front donor surface of a single crystal silicon donor wafer.

13. The method of claim 1 , further comprising annealing the bonded structure at a temperature and for a duration sufficient to strengthen the bond between the front handle silicon nitride layer and the donor silicon dioxide layer.

14. The method of claim 1 , further comprising mechanically cleaving the bonded structure at the damage layer of the single crystal silicon donor wafer to thereby prepare a cleaved structure comprising the single crystal silicon handle wafer, the handle silicon dioxide layer, the handle silicon nitride layer, the donor silicon dioxide layer, and a single crystal silicon device layer.

15. A method of preparing a multilayer structure, the method comprising the following steps in order:
(a) forming a front handle silicon dioxide layer on a front handle surface of a single crystal silicon handle wafer, wherein the single crystal silicon handle wafer comprises two major, generally parallel surfaces, one of which is the front handle surface of the single crystal silicon handle wafer and the other of which is the back handle surface of the single crystal silicon handle wafer, a circumferential edge joining the front handle surface and the back handle surface of the single crystal silicon handle wafer, a central plane between the front handle surface and the back handle surface of the single crystal silicon handle wafer, and a bulk region between the front and back handle surfaces of the single crystal silicon handle wafer;
(b) forming a front handle silicon nitride layer on the front handle silicon dioxide layer;
(c) annealing the single crystal silicon handle wafer comprising the front handle silicon dioxide layer and the front handle silicon nitride layer at a temperature of at least about 900° C. and duration between about 10 minutes and about 10 hours sufficient to densify the front handle silicon dioxide layer, the front handle silicon nitride layer, or both; and
(d) bonding the front handle silicon nitride layer to a donor silicon dioxide layer on a front donor surface of a single crystal silicon donor wafer to thereby form a bonded structure, wherein the single crystal silicon donor wafer comprises two major, generally parallel surfaces, one of which is the front donor surface of the single crystal silicon donor wafer and the other of which is the back donor surface of the single crystal silicon donor wafer, a circumferential edge joining the front donor surface and the back donor surface of the single crystal silicon donor wafer, a central plane between the front donor surface and the back donor surface of the single crystal silicon donor wafer, and a bulk region between the front and back donor surfaces of the single crystal silicon donor wafer, and further wherein the single crystal silicon donor wafer comprises a damage layer formed by ion implantation.

16. The method of claim 15 , wherein the front handle silicon dioxide layer is formed on the front handle surface of the single crystal silicon handle wafer and the back handle silicon dioxide layer on a back handle surface of the single crystal silicon handle wafer by plasma enhanced chemical vapor deposition.

17. The method of claim 15 , wherein the front handle silicon nitride layer is formed on the front handle silicon dioxide layer and the back handle silicon

Assignees

• Sunedison Semiconductor Ltd Uen201334164H

Inventors

• Erk Henry Frank
• Kweskin Sasha
• Libbert Jeffrey L
• Bulsara Mayank

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title