Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10475640-B2
Application number	US-201816137583-A
Country	US
Kind code	B2
Filing date	Sep 21, 2018
Priority date	Jun 5, 2015
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate comprising a MEMS region and a connection region thereon;
providing a dielectric layer disposed on said substrate in said connection region;
providing a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer to prevent wet etchants from contacting said dielectric layer underneath said connection region;
providing a connection pad disposed on said poly-silicon layer;
providing a passivation layer covering said dielectric layer, wherein the passivation layer comprises an opening that exposes said connection pad and a transition region between said connection pad and said passivation layer; and
providing a conductive layer conformally covering said connection pad and said poly-silicon layer in said transition region.

2. The method of claim 1 , wherein said conductive layer comprises a single layer comprising metal, conductive oxide, conductive nitride or combination thereof.

3. The method of claim 1 , wherein said conductive layer comprises multiple layers comprising metal, conductive oxide, conductive nitride or combination thereof.

4. The method of claim 1 , wherein said MEMS region comprises a plurality of sealed micromachined mesh membranes carried by said substrate.

Assignees

• United Microelectronics Corp

Inventors

• Chen Yan-Da
• Chen Weng Yi
• Hsu Chang-Sheng
• Wang Kuan-Yu
• Lin Yuan Sheng

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10P14/60 Primary

  of insulating materials · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B81C2201/014

  by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal · CPC title