Method and apparatus for system resource management

Patent metadata

Field	Value
Publication number	US-10474574-B2
Application number	US-201615781316-A
Country	US
Kind code	B2
Filing date	Dec 2, 2016
Priority date	Dec 2, 2015
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

First claim

The invention claimed is:

1. A method for operating an electronic device, the method comprising:
reading a first part of data from a first memory;
determining a first padding address based on an address of at least one byte in a border area of the data from among a plurality of bytes included in the first part;
writing, in a second memory, values of the plurality of bytes and at least one value corresponding to the first padding address; and
reading a second part of the data from the first memory.

2. The method of claim 1 , further comprising:
determining a second padding address based on an address of at least one byte in the border area of the data from among a plurality of bytes included in the second part; and
writing, in the second memory, values of the plurality of bytes included in the second part and at least one value corresponding to the second padding address.

3. The method of claim 1 , wherein the border area of the data comprises a plurality of areas, further comprising:
determining whether each byte of the plurality of bytes included in the first part is included in a first area of the plurality of areas during a determination of whether the each byte is included in a second area of the plurality of areas.

4. The method of claim 3 , wherein the border area is divided into the plurality of areas based on a number of padding addresses required to apply a filter to at least one byte in each of the plurality of areas.

5. The method of claim 1 , wherein the border area of the data and the at least one value corresponding to the first padding address are determined based on at least one of a predetermined padding mode, an address range of the at least one byte in the border area of the data, and length information where padding is performed in each direction outside a border of the data.

6. The method of claim 5 , wherein the address range of the at least one byte in the border area of the data and the length information where padding is performed in each direction outside the border of the data are determined by a software stack.

7. The method of claim 5 , wherein the padding mode is at least one of replication, mirroring, and zero-based mode.

8. The method of claim 1 , further comprising:
applying, to the first part of the data, at least one of:
a transpose for mutually switching rows and columns of the data,
a rotation,
a saturation on values of the bytes, and
a trimming.

9. The method of claim 1 , wherein the first memory is an external memory and the second memory is an internal memory.

10. The method of claim 1 , wherein the border area is determined based on whether a padding is required to apply a filter to at least one byte in the border area.

11. An electronic device comprising:
a first memory;
a second memory; and
at least one processor, wherein the at least one processor is configured to:
read a first part of data from the first memory,
determine a first padding address based on an address of at least one byte in a border area of the data from among a plurality of bytes included in the first part,
write, in the second memory, values of the plurality of bytes and a at least one value corresponding to the first padding address, and
read a second part of the data from the first memory.

12. The device of claim 11 , wherein the at least one processor is further configured to:
determine a second padding address based on an address of a byte in the border area of the data from among a plurality of bytes included in the second part, and
write, in the second memory, values of the plurality of bytes included in the second part and at least one value corresponding to the second padding address.

13. The device of claim 11 , wherein the border area of the data comprises a plurality of areas, and the at least one processor is further configured to:
determine whether each byte of the plurality of bytes included in the first part is included in a first area of the plurality of areas during a determination of whether the each byte is included in a second area of the plurality of areas.

14. The device of claim 13 , wherein the border area is divided into the plurality of areas based on a number of padding addresses required to apply filter to at least one byte in each of the plurality of areas.

15. The device of claim 11 , wherein the border area of the data and the at least one value corresponding to the first padding address are determined based on at least one of a predetermined padding mode, an address range of the at least one byte in the border area of the data, and length information where padding is performed in each direction outside the border of the data.

16. The device of claim 15 , wherein the padding mode is at least one of replication, mirroring, and zero-based mode.

17. The device of claim 15 , wherein the address range of the at least one byte in the border area of the data and the length information where padding is performed in each direction outside the border of the data are determined by a software stack.

18. The device of claim 11 , wherein the at least one processor is further configured to apply, to the first part of the data, at least one of:
a transpose for mutually switching rows and columns of the data,
a rotation,
a saturation on values of the bytes, and
a trimming.

19. The device of claim 11 , wherein the first memory is an external memory and the second memory is an internal memory.

20. The device of claim 11 , wherein the border area is determined based on whether a padding is required to apply a filter to at least one byte in the border area.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Changhun
• Kim Wonjin
• Kim Hyunsik
• Moon Sunho
• Ahn Minwook
• Kim Rakie
• Cho Kyoungsoo
• Saunshi Nikunj
• Kapoor Parichay
• Agarwal Pankaj
• Kim Won-Sub
• Kim Jin-Hyo
• Kim Hyunghoon
• Oh Jisu
• Lee Keongho
• Lee Seung-Beom
• Lee Jinseok
• Jang Dong-Gi
• Jo Subin
• Kansal Apoorv

Classifications

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F9/50

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F12/0646 Primary

  Configuration or reconfiguration · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/0822

  Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831) · CPC title