Apparatus and method for down conversion of data types

Patent metadata

Field	Value
Publication number	US-10474463-B2
Application number	US-201113997006-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.

First claim

We claim:

1. A processor comprising:
decode circuitry to decode a single instruction specifying a masking operation and one of truncation and saturation to be performed to a plurality of source values using the single instruction, and wherein the single instruction indicates data types of the source and destination values, wherein the data types are selected from a set including quadword, doubleword, word, and byte; and
an execution unit, responsive to the single instruction decoding, to
read a source operand value from the plurality of source values in a source location to be down-converted to a down-converted value and stored as a respective data element in a destination location;
read a mask register bit stored in a mask register corresponding to the source operand value, the mask register bit indicating whether to perform the masking operation or a conversion operation on the source operand value;
if the mask register bit indicates that the masking operation is to be performed, then perform the masking operation and store results of the masking operation in the destination location, wherein the masking operation is, as indicated by the single instruction, one of:
setting the bits of the respective data element in the destination location all equal to zero, and
maintaining existing values previously stored in the respective data element in the destination location; and

if the mask register bit indicates that a masking operation is not to be performed, then down-convert the source operand value and store the down-converted value in the destination location, wherein a first number of bits in the source location is bigger than a second number of bits of the respective data element in the destination location, and wherein the down-converting is one of truncation, signed saturation, and unsigned saturation as indicated by the single instruction,
wherein the execution unit repeats the operations for each of the plurality of source values.

2. The processor as in claim 1 wherein the destination location is within a destination register.

3. The processor as in claim 1 wherein the destination location is within a memory.

4. The processor as in claim 1 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value.

5. A method to execute one or more instructions, performing operations comprising:
decoding a single instruction specifying a masking operations and one of truncation and saturation to be performed to a plurality of source operand values using the single instruction, and wherein the single instruction indicates data types of the source and destination operand values, wherein the data types are selected from a set including quadword, doubleword, word, and byte;
in response to the decoding of the single instruction,
reading a source operand value from the plurality of source operand values in a source location to be down-converted to a down-converted value and stored as a respective data element in a destination location;
reading a mask register bit stored in a mask register corresponding to the source operand value, the mask register bit indicating whether to perform the masking operation or a conversion operation on the source operand value;
if the mask register bit indicates that the masking operation is to be performed, then performing the masking operation and storing results of the masking operation in the destination location, wherein the masking operation is, as indicated by the single instruction, one of:
setting the bits of the respective data element in the destination location all equal to zero, and
maintaining existing values previously stored in the respective data element in the destination location; and

if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the destination location, wherein a first number of bits in the source location is bigger than a second number of bits of the respective data element in the destination location, wherein the down-converting is one of truncation, signed saturation, and unsigned saturation as indicated by the single instruction,
wherein the execution unit repeats the operations for each of the plurality of source values.

6. The method as in claim 5 wherein the destination location is within a destination register.

7. The method as in claim 5 wherein the destination location is within a memory.

8. The method as in claim 5 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value.

9. A computer system comprising:
a processor and non-transitory machine-readable medium including one or more instructions, which when executed by the processor, causing the computer system to perform:
decoding a single instruction specifying a masking operation and one of truncation or saturation to be performed to a plurality of source values using the single instruction, and wherein the single instruction indicates data types of the source and destination values, wherein the data types are selected from a set including quadword, doubleword, word, and byte;
in response to the decoding of the single instruction, reading a source operand value from the plurality of source values in a source location to be down-converted to a down-converted value and stored as a respective data element in a destination location;
reading a mask register bit stored in a mask register corresponding to the source operand value, the mask register bit indicating whether to perform the masking operation or a conversion operation on the source operand value;
if the mask register bit indicates that the masking operation is to be performed, then performing the masking operation and storing results of the masking operation in the destination location, wherein the masking operation is, indicated by the single instruction, one of:
setting the bits of the respective data element in the destination location all equal to zero, and
maintaining existing values previously stored in the respective data element in the destination location; and

if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the destination location, wherein a first number of bits in the source location is bigger than a second number of bits of the respective data element in the destination location, wherein the down-converting is one of truncation, signed saturation, and unsigned saturation as indicated by the single instruction,
wherein the execution unit repeats the operations for each of the plurality of source values.

10. The computer system as in claim 9 wherein the destination location is within a destination register.

11. The computer system as in claim 9 wherein the destination location is within a memory.

12. The computer system as in claim 9 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value.

Assignees

• Ould Ahmed Vall Elmoustapha
• Valentine Robert
• Uliel Tal
• Corbal Jesus
• Sperber Zeev
• Gradstein Amit
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Valentine Robert
• Uliel Tal
• Corbal Jesus
• Sperber Zeev
• Gradstein Amit

Classifications

• G06F9/30101 Primary

  Special purpose registers · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30038

  using a mask · CPC title