Write tracking for memories

Patent metadata

Field	Value
Publication number	US-10474389-B2
Application number	US-201615201981-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Jul 5, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

First claim

The invention claimed is:

1. A method comprising:
storing, in a write tracking buffer, an entry associated with a write request that is bound for a memory, the entry indicating progress of completion of the write request;
determining an access pattern of the memory, wherein the access pattern indicates a high or a low write bandwidth of the memory based on how full the write tracking buffer is;
responsive to determining that the access pattern indicates the low write bandwidth, allowing write suspension to a bank of the memory with which the write request is associated;
determining that the write request will complete within a threshold length of time;
in response to determining that the write request will complete within the threshold length of time, disallowing the write suspension to the bank of the memory and executing the write request;
while execution of the write request is in-progress, receiving a read request associated with the bank of memory;
responsively suspending the write request that the execution of which is in-progress if the access pattern indicates the low write bandwidth;
allowing the read request to complete; and
after completion of the read request, resuming the execution of the write request; and

completing the write request.

2. The method of claim 1 comprising:
storing, in the write tracking buffer, an entry corresponding to the read request.

3. The method of claim 1 comprising:
determining a level of write suspension aggressiveness based on the memory access pattern; and
determining, based on the write suspension aggressiveness, whether to: disallow suspension of the write request, allow suspension of the write request, or disallow suspension of the write request if the write request will complete in a threshold amount of time.

4. The method of claim 1 , comprising:
determining the access pattern based on a number of entries stored in the write tracking buffer.

5. The method of claim 1 comprising:
responsive to determining that the access pattern indicates the high write bandwidth:
indicating that the write request is un-suspendable;
freeing, from the write tracking buffer, the entry associated with the write request;
receiving a read request associated with a bank of memory; and
completing the write request before allowing the read request to execute.

6. A system comprising:
a memory;
a memory controller comprising a write tracking buffer, the memory controller to:
receive a write request bound for the memory;
store an entry associated with the write request in the write tracking buffer, the entry indicating progress of completion of the write request;
determine an access pattern of the memory, wherein the access pattern indicates a high or a low write bandwidth of the memory based on how full the write tracking buffer is;
responsive to determining that the access pattern indicates the low write bandwidth, allow write suspension to a bank of the memory with which the write request is associated;
determine that the write request will complete within a threshold length of time;
in response to determining that the write request will complete within the threshold length of time, disallow the write suspension to the bank of the memory and execute the write request;
while execution of the write request is in-progress, receive a read request associated with the bank of memory;
responsively suspend the write request that the execution of which is in-progress if the access pattern indicates the low write bandwidth;
allow the read request to complete;
after completion of the read request, resume the execution of the write request; and

completing the write request.

7. The system of claim 6 , the memory controller to:
determine a level of write suspension aggressiveness based on the memory access pattern; and
determine, based on the writes suspension aggressiveness, whether to: disallow suspension of the write request, allow suspension of the write request, or disallow suspension of the write request if the write request will complete in a threshold amount of time.

8. The system of claim 6 , the memory controller to:
responsive to determining that the memory access pattern uses the high write bandwidth
indicate, in bank status information associated with a same bank of memory as the write, that the write is un-suspendable;
free, from the write tracking buffer, the entry associated with the write;
receive a read request associated with the same bank of the memory as the write request; and
complete the write request before allowing the read request to execute.

9. The system of claim 6 ,
wherein to determine the memory access pattern, the memory controller to:
determine the memory access pattern based on a number of entries stored in the write tracking buffer.

10. A non-transitory machine-readable storage medium encoded with instructions, the instructions that, when executed, cause a processor to:
receive a write request bound for a memory;
store an entry associated with the write request in a write tracking buffer, the entry indicating progress of completion of the write request;
determine, based on a number of entries stored in the write tracking buffer, an access pattern of the memory, wherein the access pattern indicates a high or a low write bandwidth of the memory;
responsive to determining that the access pattern indicates the low write bandwidth, allow write suspension to a bank of the memory with which the write request is associated;
determine that the write request will complete within a threshold length of time;
in response to determining that the write request will complete within the threshold length of time, disallow the write suspension to the bank of the memory and execute the write request;
while execution of the write request is in-progress, receive a read request associated with the bank of memory;
responsively suspend the write request that the execution of which is in-progress if the access pattern indicates the low write bandwidth;
allow the read request to complete; and
after completion of the read request, resume the execution of the write request; and

complete the write request.

11. The non-transitory computer-readable storage medium of claim 10 comprising instructions that, when executed, cause the processor to:
responsive to determining that the access pattern indicates high write bandwidth:
indicate that the write request is un-suspendable;
free, from the write tracking buffer, the entry associated with the write request;
receive a read request associated with a bank of memory; and
complete the write request before allowing the read request to execute.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Lesartre Gregg B
• Birk Brian S
• Orth Joseph F
• Ray Harvey
• Warner Craig

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F3/0673

  Single storage device · CPC title