Memory controller, memory system including the same and operation method of memory controller

Patent metadata

Field	Value
Publication number	US-10474376-B2
Application number	US-201715598418-A
Country	US
Kind code	B2
Filing date	May 18, 2017
Priority date	Jul 18, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.

First claim

What is claimed is:

1. An operating method of a memory controller, comprising:
determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and
determining a distribution pattern in which multiple units of data of the physical page are distributed to the plurality of memory devices using the logical address, each of the multiple units of data having a different data changing rate and at least two of the multiple units of data having a high data changing rate relative to remaining units of data of the multiple units of data;
wherein each of the multiple units of data is one of a first type of data and a second type of data,
wherein the distribution pattern identifies, for each unit of data, its type and the memory device, among the plurality of memory devices, in which it is stored, and
wherein the distribution pattern is periodically changed using address mapping information to maintain uniform distribution of the at least two data units having a high data changing rate among the plurality of memory devices.

2. The operating method of claim 1 , wherein the mapping of the logical address to the physical address is changed when the number of times that a specific operation is performed in the plurality of memory devices reaches a threshold value.

3. The operating method of claim 2 , wherein the specific operation comprises at least one of a write operation and an erase operation.

4. The operating method of claim 1 , wherein at least one bit of the logical address is used in determining the distribution pattern.

5. The operating method of claim 1 , wherein a certain positional number of a logical page corresponding to the physical page are used in the determining of the distribution pattern.

6. A memory system comprising:
a plurality of memory devices suitable for being accessed by a physical address; and
a memory controller suitable for controlling the memory devices,
wherein the memory controller comprises:
an address mapping circuit suitable for mapping a logical address to the physical address; and
a data distribution circuit suitable for determining a distribution pattern in which multiple units of data of a physical page to be accessed in the plurality of memory devices using the physical address are distributed to the plurality of memory devices using the logical address, each of the multiple units of data having a different data changing rate and at least two of the multiple units of data having a high data changing rate relative to remaining units of data of the multiple units of data;
wherein each of the multiple units of data is one of a first type of data and a second type of data,
wherein the distribution pattern identifies, for each unit of data, its type and the memory device, among the plurality of memory devices, in which it is stored, and
wherein the distribution pattern is periodically changed using address mapping information to maintain uniform distribution of the at least two data units having a high data changing rate among the plurality of memory devices.

7. The memory system of claim 6 , wherein the mapping of the logical address to the physical address is changed when the number of times that a specific operation is performed in the plurality of memory devices reaches a threshold value.

8. The memory system of claim 7 , wherein the specific operation comprises at least one of a write operation and an erase operation.

9. The memory system of claim 6 , wherein the data distribution circuit determines the distribution pattern based on some bits of the logical address.

10. The memory system of claim 6 , wherein the data distribution circuit determines the distribution pattern based on a certain positional number of a logical page corresponding to the physical page.

11. The memory system of claim 6 , wherein the plurality of memory devices shares an address channel and a command channel and each of the plurality of memory devices has an independent data channel.

12. The memory system of claim 6 , wherein the memory controller further comprises:
a host interface suitable for communicating with a host;
a scheduler suitable for determining a sequence of operations to be instructed to the plurality of memory devices;
a command generator suitable for generating a command to be applied to the plurality of memory devices;
an error correction circuit suitable for correcting an error of data read from the plurality of memory devices; and
a memory interface suitable for communicating with the plurality of memory devices.

13. A memory controller controlling a plurality of memory devices accessed by a physical address, the memory controller comprising:
an address mapping circuit suitable for mapping a logical address to the physical address; and
a data distribution circuit suitable for determining a distribution pattern in which multiple units of data of a physical page to be accessed in the plurality of memory devices using the physical address are distributed to the plurality of memory devices using the logical address, each of the multiple units of data having a different data changing rate and at least two of the multiple units of data having a high data changing rate relative to remaining units of data of the multiple units of data;
wherein each of the multiple units of data is one of a first type of data and a second type of data,
wherein the distribution pattern identifies, for each unit of data, its type and the memory device, among the plurality of memory devices, in which it is stored, and
wherein the distribution pattern is periodically changed using address mapping information to maintain uniform distribution of the at least two data units having a high data changing rate among the plurality of memory devices.

14. The memory controller of claim 13 , wherein the mapping of the logical address to the physical address is changed when the number of times that a specific operation is performed in the plurality of memory devices reaches a threshold value.

15. The memory controller of claim 14 , wherein the specific operation comprises at least one of a write operation and an erase operation.

16. The memory controller of claim 13 , wherein the data distribution circuit determines the distribution pattern based on at least one bit of the logical address.

17. The memory controller of claim 13 , wherein the data distribution circuit determines the distribution pattern based on a certain positional number of a logical page corresponding to the physical page.

18. The memory controller of claim 13 , further comprising:
a host interface suitable for communicating with a host;
a scheduler suitable for determining a sequence of operations to be instructed to the plurality of memory devices;
a command generator suitable for generating a command to be applied to the plurality of memory devices;
an error correction circuit suitable for correcting an error of data read from the plurality of memory devices; and
a memory interface suitable for communicating with the plurality of memory devices.

19. The memory controller of claim 18 , wherein the memory interface is suitable for:
transferring a command to the plurality of memory devices through a command channel shared by the plurality of memory devices,
transferring the physical address to the plurality of memory devices through an address channel shared by the plurality of memory devices, and
sending and receiving data to and from the plurality of memory devices through a plurality of da

Assignees

• Sk Hynix Inc

Inventors

• Xu Jing-Zhe
• Kwon Jung-Hyun
• Lee Sung-Eun
• Lee Jae-Sun
• JO Sang-Gu

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title