Thin film transistor and display device including the same

US10473989B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10473989-B2
Application numberUS-201514866242-A
CountryUS
Kind codeB2
Filing dateSep 25, 2015
Priority dateJan 22, 2015
Publication dateNov 12, 2019
Grant dateNov 12, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A thin film transistor (TFT) and a display device including the same capable of displaying an image having a uniform luminance are provided, the TFT including a gate electrode; a gate insulating layer disposed on the gate electrode; a semiconductor layer disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor layer while being spaced apart from one another; and a protective layer disposed on the source electrode and the drain electrode and having a contact hole through which a portion of the drain electrode is exposed, wherein the drain electrode includes a first drain electrode overlapping a portion of the gate electrode, a second drain electrode extending from the first drain electrode and having a portion exposed through the contact hole, and a third drain electrode branched from the first drain electrode to be spaced apart from the second drain electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin film transistor (TFT), comprising: a gate electrode; a gate insulating layer disposed on the gate electrode; a semiconductor layer disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor layer while being spaced apart from one another; and a protective layer disposed on the source electrode and the drain electrode and having a contact hole through which a portion of the drain electrode is exposed, wherein the drain electrode comprises: a first portion of the drain electrode overlapping a portion of the gate electrode, a second portion of the drain electrode extending from the first portion of the drain electrode, comprising an outer circumference in plan view, and comprising a portion exposed through the contact hole, and a third portion of the drain electrode branched from the first portion of the drain electrode and spaced apart from the outer circumference of the second portion of the drain electrode, wherein the first portion of the drain electrode and the third portion of drain electrode form a closed ring shape in a plan view that surrounds the second portion of the drain electrode. 2. The TFT of claim 1 , wherein the second portion of the drain electrode has one of a circular shape and a polygonal shape. 3. The TFT of claim 1 , wherein the third portion of the drain electrode has one of a circular ring shape and a polygonal ring shape. 4. The TFT of claim 1 , wherein the third portion of the drain electrode has a width in a range of about 1.5 micrometers (μm) to about 3.0 μm. 5. The TFT of claim 1 , wherein the third portion of the drain electrode is disposed to be spaced apart from the outer circumference of the second portion of the drain electrode by an interval in a range of about 3.0 μm to about 6.0 μm. 6. The TFT of claim 1 , wherein the third portion of the drain electrode is disposed more adjacently to the gate electrode than the second portion of the drain electrode is to the gate electrode. 7. The TFT of claim 1 , further comprising an ohmic contact layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode. 8. A display device comprising: a first substrate; a gate line disposed on the first substrate; a data line disposed to intersect the gate line; a thin film transistor (TFT) connected to the gate line and the data line; and a pixel electrode connected to the TFT, wherein the TFT comprises: a gate electrode branched from the gate line, a source electrode branched from the data line, and a drain electrode connected to the pixel electrode, and the drain electrode comprises: a first portion of the drain electrode overlapping a portion of the gate electrode, a second portion of the drain electrode extending from the first portion of the drain electrode, comprising an outer circumference in plan view, and connected to the pixel electrode, and a third portion of the drain electrode branched from the first portion of the drain electrode and spaced apart from the outer circumference of the second portion of the drain electrode, wherein the first portion of the drain electrode and the third portion of the drain electrode from a closed ring shape in a plan view that surrounds the second portion of the drain electrode. 9. The display device of claim 8 , wherein the second portion of the drain electrode has one of a circular shape and a polygonal shape. 10. The display device of claim 8 , wherein the third portion of the drain electrode has one of a circular ring shape and a polygonal ring shape. 11. The display device of claim 8 , wherein the third portion of the drain electrode has a width in a range of about 1.5 micrometers (μm) to about 3.0 μm. 12. The display device of claim 8 , wherein the third portion of the drain electrode is disposed to be spaced apart from the outer circumference of the second portion of the drain electrode by an interval in a range of about 3.0 μm to about 6.0 μm. 13. The display device of claim 8 , wherein the third portion of the drain electrode is disposed more adjacently to the gate electrode than the second portion of the drain electrode is to the gate electrode. 14. The display device of claim 8 , wherein the pixel electrode comprises: a horizontal stem electrode, a vertical stem electrode, and a plurality of branch electrodes extending from the horizontal stem electrode and the vertical stem electrode. 15. The display device of claim 14 , wherein the branch electrode comprises: a first branch electrode extending from the horizontal stem electrode and the vertical stem electrode in an upper left direction, a second branch electrode extending from the horizontal stem electrode and the vertical stem electrode in an upper right direction, a third branch electrode extending from the horizontal stem electrode and the vertical stem electrode in a lower left direction, and a fourth branch electrode extending from the horizontal stem electrode and the vertical stem electrode in a lower right direction. 16. The display device of claim 8 , further comprising a color filter disposed between the TFT and the pixel electrode. 17. The display device of claim 8 , further comprising: a second substrate disposed opposite to the first substrate; a common electrode disposed on the second substrate; and a liquid crystal layer interposed between the first and second substrates. 18. The display device of claim 17 , further comprising an alignment layer disposed on the first or second substrate, wherein one of the alignment layer and the liquid crystal layer includes a polymer material having an orientation.

Assignees

Inventors

Classifications

  • Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

  • Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

  • characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

  • Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence) · CPC title

  • characterised by the electrodes · CPC title

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What does patent US10473989B2 cover?
A thin film transistor (TFT) and a display device including the same capable of displaying an image having a uniform luminance are provided, the TFT including a gate electrode; a gate insulating layer disposed on the gate electrode; a semiconductor layer disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor layer while being spaced apart f…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136227. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).