Array substrate and its manufacturing method and display panel

Patent metadata

Field	Value
Publication number	US-10473965-B2
Application number	US-201715737298-A
Country	US
Kind code	B2
Filing date	Oct 20, 2017
Priority date	Aug 30, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

The present disclosure discloses an array substrate and its manufacturing method and display panel, wherein, the method for fabricating the array substrate including the steps of: providing a substrate; sequentially forming a TFT functional layer, a touch signal transmission line, a first insulating layer, a first electrode, and a second insulating layer on the substrate; forming a first via and a second via on the second insulating layer by photolithography; forming a second electrode and a metal pattern on the second insulating layer; wherein the metal pattern connects the touch signal transmission line and the first electrode through the first via, and the second electrode connects the source and/or drain through the second via. By the above-described method, the present disclosure can reduce the manufacturing process of the array substrate, thereby reducing the manufacturing cost of the array substrate.

First claim

What is claimed is:

1. An array substrate comprising a substrate, a TFT functional layer, a touch signal transmission line, a first insulating layer, a first electrode, a second insulating layer, a second electrode, and a metal pattern, wherein the substrate, the TFT functional layer, the touch signal transmission line, the first insulating layer, the first electrode and the second insulating layer are sequentially stacked, the second electrode and the metal pattern are stacked on the second insulating layer;
wherein the first electrode serves both as a common electrode and also as a touch sensor;
wherein the second insulating layer is arranged with a first via and a second via formed by photolithography, the first via comprises a first through hole extending through the second insulating layer and a second through hole, the second through hole comprises a first sub-through hole extending through the first electrode and a second sub-through hole extending through the first insulating layer, a width of the first sub-through hole is equal to a width of the second sub-through hole, a width of the first through hole is larger than the width of the first sub-through hole and the width of the second sub-through hole so that the bottom of the first through hole exposes a portion of the upper surface of the first electrode, the bottom of the second through hole exposes a portion of the upper surface of the touch signal transmission line, the second via making the source and/or drain in the TFT functional layer exposed;
wherein the second electrode and the metal pattern are fabricated using the same metal layer, the metal pattern connects the touch signal transmission line and the first electrode through the first via, the second electrode connecting the source and/or drain through the second via.

2. The array substrate according to claim 1 , wherein the touch signal transmission line, the first insulating layer, the first electrode, the second insulating layer, the second electrode and the metal pattern are fabricated by the following method:
forming a first metal layer on said TFT functional layer and patterning said first metal layer to obtain the touch signal transmission line;
forming the first insulating layer on said first metal layer;
forming a second metal layer on said first insulating layer and patterning said second metal layer to obtain the first electrode;
forming the second insulating layer on said second metal layer.

3. The array substrate according to claim 1 , wherein the first electrode, the second electrode, and the metal pattern are fabricated using ITO.

4. The array substrate according to claim 1 , wherein the TFT functional layer comprises a light-shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate, an interlayer dielectric layer, a source/drain, and a flat layer;
wherein the interlayer dielectric layer is arranged with a third via and a fourth via formed by etching, the third via exposes a source region of the active layer, the fourth via exposes a drain region of the active layer; the source electrode is connected to the source region through the third via, the drain electrode is connected to the drain region through the fourth via.

5. The array substrate according to claim 4 , wherein the TFT functional layer is fabricated by the following method:
forming a light-shielding layer on the substrate;
forming a buffer layer on the light blocking layer;
forming an active layer on the buffer layer and forming a source region and a drain region by doping;
forming a gate insulating layer on the active layer;
forming a gate on the gate insulating layer;
forming an interlayer dielectric layer on the gate electrode;
etching on the interlayer dielectric layer to form a third via and a fourth via; wherein the third via exposes the source region, the fourth via exposes the drain region;
forming a source and a drain on the interlayer dielectric layer; wherein the source is connected to the source region through the third via, the drain is connected to the drain region through the fourth via;
forming a flat layer on the source and the drain.

6. The array substrate according to claim 5 , wherein the buffer layer, the gate insulating layer, and the interlayer dielectric layer are made of an inorganic material, and the flat layer is made of an organic material.

7. The array substrate according to claim 6 , wherein the inorganic material is SiOx, SiNx, or a mixture of SiOx and SiNx.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Zheng Lihua
• Bu Huanhuan
• Yang Pan

Classifications

• H10P14/3808

  using laser beams · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title