Data output for high frequency domain

Patent metadata

Field	Value
Publication number	US-10470475-B2
Application number	US-201816197871-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	Jul 18, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

First claim

What is claimed is:

1. An apparatus comprising:
one or more memory banks configured to store data;
a data path coupled to the one or more memory banks and configured to transfer the data;
a latch configured to gate the data path based on a clock signal in the system; and
interface circuitry coupled to the data path, wherein the interface circuitry is configured to:
send an instruction to the one or more memory banks to transmit the data on the data path based on the clock signal; and
output gated data based on the clock signal, wherein the latch is configured to gate the data path to store the gated data based on the clock signal.

2. The apparatus of claim 1 , wherein the interface circuitry is configured to send the instruction in response to receiving a first rising edge of the clock signal.

3. The apparatus of claim 1 , wherein the interface circuitry is configured to output the gated data in response to receiving a second rising edge of the clock signal.

4. The apparatus of claim 1 , wherein the latch is configured to gate the data path to store the gated data in response to receiving a falling edge of the clock signal.

5. The apparatus of claim 1 , wherein the interface circuitry is configured to:
send a second instruction to the one or more memory banks to transmit second data on the data path based on an inverted clock signal; and
output gated data based on the inverted clock signal, wherein the latch is configured to gate the data path to store the gated data based on the inverted clock signal.

6. The apparatus of claim 5 , wherein the interface circuitry is configured to send the second instruction in response to receiving a first rising edge of the inverted clock signal.

7. The apparatus of claim 5 , wherein the interface circuitry is configured to output the gated data in response to a second rising edge of the inverted clock signal.

8. The apparatus of claim 5 , wherein the latch is configured to gate the data path to store the gated data in response to a first falling edge of the inverted clock signal.

9. The apparatus of claim 5 , wherein the inverted clock signal comprises an inversion of the clock signal.

10. An apparatus comprising:
one or more memory banks configured to store first data and second data;
a first data path coupled to the one or more memory banks configured to transfer the first data;
a second data path coupled to the one or more memory banks configured to transfer the second data;
a first latch configured to gate the first data path based on a clock signal in the semiconductor device;
a second latch configured to gate the second data path based on an inverted clock signal;
a first set of logic gates that receives and combines outputs of the first latch and the second latch and provides the combined outputs of the first latch and the second latch to a first transistor coupled to a positive power supply;
a third latch configured to gate the first data path based on the clock signal;
a fourth latch configured to gate the second data path based on the inverted clock signal;
a second set of logic gates that receives and combines outputs of the third latch and the fourth latch and provides the combined outputs of the third latch and the fourth latch to a second transistor coupled to a negative power supply; and
interface circuitry coupled to the one or more memory banks, the first latch, and the second latch, wherein the interface circuitry is configured to:
send a first instruction to the one or more memory banks to transmit the first data on the first data path;
send a second instruction to the one or more memory banks to transmit the second data on the second data path;
output first gated data based on the clock signal; and
output second gated data based on the inverted clock signal.

11. The apparatus of claim 10 , wherein the first gated data is gated by the first latch.

12. The apparatus of claim 10 , wherein the first gated data is gated by the third latch.

13. The apparatus of claim 10 , wherein the second gated data is gated by the second latch.

14. The apparatus of claim 10 , wherein the second gated data is gated by the fourth latch.

15. The apparatus of claim 10 , wherein the interface circuitry is configured to send the first instruction in response to receiving a first rising edge of the clock signal.

16. The apparatus of claim 10 , wherein the interface circuitry is configured to output first gated data in response to receiving a second rising edge of the clock signal.

17. The apparatus of claim 10 , wherein the interface circuitry is configured to send the second instruction in response to receiving a first rising edge of the inverted clock signal.

18. The apparatus of claim 17 , wherein the interface circuitry is configured to output second gated data in response to receiving a second rising edge of the inverted clock signal.

19. The apparatus of claim 10 , wherein the first latch is configured to gate the first data path to store the first gated data in response to receiving a first falling edge of the clock signal, and wherein the second latch is configured to gate the second data path to store the second gated data in response to receiving a first falling edge of the inverted clock signal.

20. The apparatus of claim 10 , wherein the third latch is configured to gate the first data path to store the first gated data in response to receiving a first falling edge of the clock signal, and wherein the fourth latch is configured to gate the second data path to store the second gated data in response to receiving a first falling edge of the inverted clock signal.

21. A tangible, non-transitory, machine-readable-medium, comprising machine-readable instructions that, when executed by a processor, cause the processor to:
receive a first rising edge of a clock signal;
send a first instruction to transmit data on a first data path in response to receiving the first rising edge of the clock signal;
receive a falling edge of the clock signal;
gate the first data path to store first gated data in response to receiving the falling edge of the clock signal;
receive a second rising edge of the clock signal; and
output the first gated data in response to receiving the second rising edge of the clock signal.

22. The tangible, non-transitory, machine-readable-medium of claim 21 , comprising machine-readable instructions that, when executed by the processor, cause the processor to:
receive a first rising edge of an inverted clock signal;
send a second instruction to transmit data on a second data path in response to receiving the first rising edge of the inverted clock signal;
receive a falling edge of the inverted clock signal;
gate the second data path to store second gated data in response to receiving the falling edge of the inverted clock signal;
receive a second rising edge of the inverted clock signal; and
output the second gated data in response to receiving the second rising edge of the inverted clock signal.

Assignees

• Micron Technology Inc

Inventors

• Mazumder Kallol
• Bae Myung-Ho

Classifications

• G01N33/18

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• G01N21/33

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• C02F2209/02

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• Y02W10/37

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• C02F2201/009

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