Power-conserving clocking for scanning sensors

Patent metadata

Field	Value
Publication number	US-10469782-B2
Application number	US-201715713003-A
Country	US
Kind code	B2
Filing date	Sep 22, 2017
Priority date	Sep 27, 2016
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A time delay and integration charge coupled device includes an array of pixels and a clock generator. The array of pixels is distributed in a scan direction and a line direction perpendicular to the scan direction in which at least some of the pixels of the array include three or more gates aligned in the scan direction. The clock generator provides clocking signals to transfer charge along the scan direction between two or more pixel groups including two or more pixels adjacent in the scan direction. The clocking signals include phase signals to transfer the charge to an adjacent pixel group along the scan direction at a rate corresponding to the velocity of the target by driving the gates of the two or more pixel groups and generating a common potential well per pixel group for containing charge generated in response to incident illumination.

First claim

What is claimed:

1. A time delay and integration charge coupled device, comprising:
an array of pixels distributed in a scan direction and a line direction perpendicular to the scan direction, wherein at least some of the pixels of the array include three or more gates aligned in the scan direction; and
a clock generator configured to generate clocking signals to transfer charge along the scan direction between two or more pixel groups adjacent in the scan direction, wherein a pixel group of the pixel groups includes two or more pixels adjacent in the scan direction, wherein the clocking signals include phase signals to drive the gates of the two or more pixel groups, wherein the clocking signals generate a common potential well per pixel group for containing charge generated in response to incident illumination, wherein the clocking signals transfer the charge to an adjacent pixel group along the scan direction at a rate corresponding to a velocity of a target.

2. The time delay and integration charge coupled device of claim 1 , wherein the clocking signals comprise:
independent phase signals for the gates of the two or more pixels in the pixel groups.

3. The time delay and integration charge coupled device of claim 2 , wherein a number of the independent phase signals equals a number of gates in each pixel group.

4. The time delay and integration charge coupled device of claim 1 , wherein the pixels of the array include three gates aligned in the scan direction, wherein the two or more pixels of the pixel groups include two pixels, wherein the clocking signals comprises:
six independent phase signals for the gates of the two pixels in the pixel groups.

5. The time delay and integration charge coupled device of claim 1 , wherein the pixels of the array include three gates aligned in the scan direction, wherein the two or more pixels of the pixel groups include three pixels, wherein the clocking signals comprises:
nine independent phase signals for the gates of the two pixels in the pixel groups.

6. The time delay and integration charge coupled device of claim 1 , wherein the pixels of the array include four gates aligned in the scan direction, wherein the two or more pixels of the pixel groups include two pixels, wherein the clocking signals comprises:
eight independent phase signals for the gates of the two pixels in the pixel groups.

7. The time delay and integration charge coupled device of claim 1 , wherein the clocking signals minimize a net return current for the pixel groups within a selected tolerance.

8. The time delay and integration charge coupled device of claim 7 , wherein the phase signals comprise:
sinusoidal phase signals.

9. The time delay and integration charge coupled device of claim 7 , wherein the pixels of the array include n gates, wherein the two or more pixels of the pixel groups include m pixels, wherein the clocking signals include phase signals, Vk, of the form Vk=sin(ωt÷2πk/(m•n)) for k=0, 1, . . . , m×n−1.

10. The time delay and integration charge coupled device of claim 1 , wherein a width of the common potential well has a width approximately equal to a single pixel of the array.

11. The time delay and integration charge coupled device of claim 1 , further comprising:
a shift register including a line of pixels distributed along the line direction, wherein at least some pixels of the shift register are configured to receive charge from the pixel groups in response to a cycle of the clocking signals; and
a register signal generator configured to transfer charge from the shift register to an output amplifier to clear the shift register, wherein the register signal generator is configured to clear the shift register after each cycle of voltage signals.

12. The time delay and integration charge coupled device of claim 1 , wherein the clock generator is further configured to dynamically adjust a number of pixels in the pixel groups.

13. The time delay and integration charge coupled device of claim 12 , wherein the clock generator is further configured to dynamically adjust the number of pixels in the pixel groups to meet a power consumption specification.

14. The time delay and integration charge coupled device of claim 12 , wherein the clock generator is further configured to dynamically adjust the number of pixels in the pixel groups to meet an imaging resolution specification.

15. An imaging system, comprising:
an illumination source configured to generate an illumination beam;
a sample translation device configured translate a target object along a scan direction;
a set of illumination optics configured to direct the illumination beam to the target object disposed on the sample translation device;
a time delay and integration detector, the detector comprising:
an array of pixels distributed in the scan direction and a line direction perpendicular to the scan direction; and
a clock generator configured to generate clocking signals to transfer charge along the scan direction between two or more pixel groups adjacent in the scan direction, wherein a pixel group of the pixel groups includes two or more pixels adjacent in the scan direction, wherein the clocking signals include phase signals to drive gates of the two or more pixel groups, wherein the clocking signals generate a common potential well per pixel group for containing charge generated in response to incident illumination from the target object, wherein the clocking signals transfer the charge to an adjacent pixel group along the scan direction at a rate corresponding to a velocity of the target object;

a set of collection optics configured to generate an image of the target object on the detector in response to the incident illumination from the target object; and
a controller communicatively coupled to the detector and the sample translation device, the controller including one or more processors configured to execute instructions configured to cause the one or more processors to synchronize the transfer of charge along the scan direction in the detector with motion of the target object along the scan direction.

16. The imaging system of claim 15 , wherein synchronizing the transfer of charge along the scan direction in the detector with motion of the target object along the scan direction comprises:
synchronizing, via the sample translation device, a translation velocity of the target object to the transfer of charge along the scan direction in the detector.

17. The imaging system of claim 15 , wherein synchronizing the transfer of charge along the scan direction in the detector with motion of the target object along the scan direction comprises:
synchronizing, via the detector, a rate of the transfer of charge along the scan direction in the detector to a translation velocity of the target object on the sample translation device.

18. The imaging system of claim 15 , wherein the clocking signals comprise:
independent phase signals for the gates of the two or more pixels in the pixel groups.

19. The imaging system of claim 18 , wherein a number of the independent phase signals equals a number of gates in each pixel group.

20. The imaging system of claim 15 , wherein the pixels of the array include three gates aligned in the scan direction, wherein the two or more pixels of the pixel groups include two pixels, wherein the clocking signals comprises:
six independent phase signals for the gates of the two pixels in the pixel groups.

21. The time delay and integration charge coupled de

Assignees

• Kla Tencor Corp

Inventors

• Brown David L

Classifications

• H04N25/713

  Transfer or readout registers; Split readout registers or multiple readout registers · CPC title

• H04N25/71 Primary

  Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors · CPC title

• H04N25/711

  Time delay and integration [TDI] registers; TDI shift registers · CPC title

• H04N25/72

  using frame transfer [FT] · CPC title

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title