Variable delay

Patent metadata

Field	Value
Publication number	US-10469091-B2
Application number	US-201715711924-A
Country	US
Kind code	B2
Filing date	Sep 21, 2017
Priority date	Sep 21, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe generating a compensation current based on a number of edges of pulses propagating through a variable delay line including multiple delay elements. The number of edges propagating through the variable delay is determined by computing a difference between a number of edges entering the variable delay line and a number of edges exiting the variable delay line. The compensation current is derived from a mirrored version of the current of the control signal of the PLL. Thus, the techniques and systems in this disclosure provide accurate and repeatable control of a variable delay line over variations in temperature and process using low-power circuits. Furthermore, the input signal to the variable delay line may be asynchronous with respect to a system clock or a reference signal of the PLL.

First claim

What is claimed is:

1. A method of implementing a variable delay, the method comprising:
generating a control signal that adjusts a voltage-controlled oscillator (VCO) of a phase-locked loop (PLL) responsive to operation of the PLL;
determining a number of edges of an input signal propagating through a variable delay line comprising a plurality of delay elements, the determining comprising:
counting a number of edges of the input signal entering the variable delay line to produce a first count;
counting a number of edges exiting the variable delay line to produce a second count; and
determining a difference between the second count and the first count using a subtraction operation to determine the number of edges of the input signal propagating through the variable delay line;

adjusting a delay of each delay element of the plurality of delay elements based on the control signal and the number of edges of the input signal propagating through the variable delay line; and
delaying the input signal using the variable delay line.

2. The method as recited in claim 1 , further comprising:
generating a compensation current proportional to the number of edges of the input signal propagating through the variable delay line, wherein
the adjusting the delay based on the number of edges of the input signal propagating through the variable delay line comprises adjusting the delay of each delay element of the plurality of delay elements using the compensation current.

3. The method as recited in claim 2 , further comprising:
buffering the control signal to form a buffered control signal, wherein
the adjusting the delay of each delay element of the plurality of delay elements using the compensation current comprises injecting the compensation current into a circuit node coupled to the buffered control signal; and
the compensation current compensates for current consumed by the variable delay line by propagating the edges of the input signal to resist a voltage change in the buffered control signal.

4. The method as recited in claim 2 , wherein the generating the compensation current comprises:
mirroring a current of the control signal to form a mirrored current;
providing the mirrored current to a digital-to-analog converter (DAC) as a reference current; and
converting the number of edges of the input signal propagating through the variable delay line with the DAC based on the reference current to produce the compensation current.

5. The method as recited in claim 4 , further comprising:
adjusting at least one of the mirrored current, the reference current, the compensation current, or the control signal based on calibration data indicative of a determinable relationship between the VCO and the plurality of delay elements.

6. The method as recited in claim 5 , wherein the determinable relationship includes a difference in the delay of each delay element of the plurality of delay elements and another delay of each delay element of an additional plurality of delay elements comprising the VCO.

7. The method as recited in claim 1 , wherein:
the VCO includes an additional plurality of delay elements; and
each delay element of the additional plurality of delay elements of the VCO and each delay element of the plurality of delay elements of the variable delay line have a substantially similar design to produce a substantially similar delay during operation.

8. The method as recited in claim 1 , wherein the input signal is asynchronous with respect to a reference signal of the PLL.

9. The method as recited in claim 1 , wherein the input signal comprises pulses generated for at least one sensor configured to detect a fingerprint.

10. The method as recited in claim 1 , further comprising:
adjusting a beamformed signal using one or more outputs of the plurality of delay elements of the variable delay line.

11. The method as recited in claim 1 , wherein the PLL and the plurality of delay elements of the variable delay line are embodied on a System-on-a-Chip (SoC).

12. The method as recited in claim 1 , wherein a voltage swing of the input signal is larger than a voltage swing of the control signal.

13. The method as recited in claim 1 , further comprising:
selecting an output of one delay element of the plurality of delay elements as a delayed input signal; and
level-shifting the delayed input signal.

14. The method as recited in claim 1 , wherein each delay element of the plurality of delay elements comprises at least one inverter.

15. The method as recited in claim 1 , wherein the adjusting comprises:
adjusting the delay of each delay element of the plurality of delay elements by changing at least one of:
a reference signal of the PLL to adjust the control signal; or
a divider ratio of the PLL to adjust the control signal.

16. A system for delaying an input signal, the system comprising:
a phase-locked loop (PLL) configured to generate a control signal that adjusts a voltage-controlled oscillator (VCO) of the PLL;
a variable delay line comprising a plurality of delay elements;
an edge compensation circuit configured to determine a number of edges of the input signal propagating through the variable delay line, the edge compensation circuit comprising:
a first counter configured to count a number of edges of the input signal entering the variable delay line to produce a first count;
a second counter configured to count a number of edges exiting the variable delay line to produce a second count; and
a subtractor configured to determine a difference between the second count and the first count to determine the number of edges of the input signal propagating through the variable delay line; and

a node configured to adjust a delay of each delay element of the plurality of delay elements based on the control signal and the number of edges of the input signal propagating through the variable delay line to delay the input signal.

17. The system as recited in claim 16 , wherein the system comprises at least one of a System-on-a-Chip (SoC) or a computing device.

18. The system as recited in claim 16 , wherein the edge compensation circuit is further configured to:
generate a compensation current proportional to the number of edges of the input signal propagating through the variable delay line; and
inject the compensation current into the node to adjust the delay of each delay element based on the number of edges of the input signal propagating through the variable delay line.

19. The system as recited in claim 18 , wherein:
the edge compensation circuit comprises a digital-to-analog converter (DAC); and
the edge compensation circuit is further configured to:
obtain a mirrored version of a current of the control signal from the PLL;
provide the mirrored version of the current to the DAC as a reference current; and
convert the number of edges of the input signal propagating through the variable delay line with the DAC based on the reference current to produce the compensation current.

20. The system as recited in claim 16 , wherein:
the VCO includes an additional plurality of delay elements; and
each delay element of the additional plurality of delay elements of the VCO and each delay element of the plurality of delay elements of the variable delay line have a substantially similar design to produce a substantially similar delay during operation.

21. A device for adjusting a variable delay, the device comprising:
a phase-locked loop (PLL) configured to generate a c

Assignees

• Qualcomm Inc

Inventors

• Roham Masoud

Classifications

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/0893

  the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop · CPC title

• H03L7/0818

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03D3/241

  the oscillator being part of a phase locked loop · CPC title