Gallium nitride (GaN) power amplifiers (PA) with angled electrodes and 100 CMOS and method for producing the same

Patent metadata

Field	Value
Publication number	US-10469041-B2
Application number	US-201815886475-A
Country	US
Kind code	B2
Filing date	Feb 1, 2018
Priority date	Feb 1, 2018
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.

First claim

What is claimed is:

1. A device comprising: a complementary metal oxide semiconductor (CMOS) transistor on a 100 silicon (Si); and a gallium nitride (GaN) high electron mobility transistor (HEMT) on a 111 Si, wherein the 100 Si and the 111 Si are contiguous; wherein the GaN HEMT comprises: a buffer layer over a portion of each surface of a V-shaped groove; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over the GaN layer; a passivation layer over the AlGaN layer; a first electrode over a portion of the passivation layer and through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode over a portion of the passivation layer and through the passivation layer down to the AlGaN layer; a dielectric layer over the 111 Si; and a metal-filled via through the dielectric layer down to at least one of the first electrode and the second electrode.

2. The device according to claim 1 , further comprising:
a protective layer over the CMOS transistor and on portions of the 100 Si;
a dielectric layer over the 100 Si and the protective layer; and
the metal-filled via through the dielectric layer and the protective layer to the CMOS transistor.

3. The device according to claim 1 , wherein the buffer layer, the GaN layer, the AlGaN layer, and the passivation layer each have vertical ends.

4. The device according to claim 1 , wherein each sidewall of the V-shaped groove has an angle of approximately 54.7 degrees, and wherein each of the first electrode and the second electrode is formed at the angle of approximately 54.7 degrees.

5. The device according to claim 1 , wherein each of the first electrode and the second electrode is formed on one sidewall of the V-shaped groove or both.

6. The device according to claim 1 , further comprising:
a second buffer layer over a remaining portion of the V-shaped groove.

7. The device according to claim 6 , further comprising:
a second GaN layer over the second buffer layer;
a second AlGaN layer over the second GaN layer; and
a second passivation layer over the second AlGaN layer.

8. A device comprising:
a first silicon (Si) layer;
a silicon germanium (SiGe) layer over the first Si layer;
a second Si layer over the SiGe layer with a trench down to the SiGe layer having angled sidewalls;
a buffer layer over a portion of each angled sidewall of the trench;
a gallium nitride (GaN) layer over the buffer layer;
an aluminum gallium nitride (AlGaN) layer over a portion of the GaN layer;
a passivation layer over the AlGaN layer;
a first electrode structure through the passivation layer and the AlGaN layer down to the GaN layer;
a second electrode structure through the passivation layer down to the AlGaN layer;
a third electrode structure through the passivation layer and the AlGaN layer down to the GaN layer and over a portion of one of the angled sidewall and the SiGe layer within the trench;
a dielectric layer over the first Si layer, filling the trench;
a device over a portion of the second Si layer proximate to the trench; and
a metal-filled via through the dielectric layer down to each of the first electrode structure, the second electrode structure and the third electrode structure.

9. The device according to claim 8 , further comprising:
a second device formed over the SiGe layer within the trench; and
a second metal-filled via through the dielectric layer down to the second device.

10. The device according to claim 8 , wherein each angled sidewall comprises 111 Si and has an angle of approximately 54.7 degrees and wherein the first Si layer and a remaining portion of the second Si layer comprise 100 Si.

Assignees

• Globalfoundries Inc

Inventors

• Stamper Anthony Kendall
• Jain Vibhor
• Campanella Pineda Humberto
• Pekarik John Joseph

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6506

  Formation of intermediate materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title