Balancing techniques and circuits for charge pumps

US10468978B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10468978-B2
Application numberUS-201715465487-A
CountryUS
Kind codeB2
Filing dateMar 21, 2017
Priority dateJul 15, 2016
Publication dateNov 5, 2019
Grant dateNov 5, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter and a negative input configured to receive a second hysteresis voltage. A first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage. A second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of pre-balancing a switched capacitor converter having a plurality of switches coupled in series, an input capacitor, an output capacitor, and a flying capacitor, the method comprising: comparing a voltage across the output capacitor to a first hysteresis voltage; upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage, discharging the output capacitor via a first current source; comparing a voltage across the input capacitor to a second hysteresis voltage; and upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage, discharging the input capacitor via a second current source. 2. The method of claim 1 , wherein the first and second hysteresis voltages are equal in magnitude. 3. The method of claim 1 , further comprising: keeping a pass switch between an input node and the input capacitor of the switched capacitor converter off while the input capacitor or the output capacitor is discharged; and turning the pass switch on after the input capacitor and the output capacitor have been discharged to respective threshold levels. 4. The method of claim 3 , further comprising, upon completing the discharge of the input capacitor and the output capacitor to respective threshold levels, providing a soft start for the switched capacitor converter by initiating a switching of the plurality of switches followed by a ramp up of an input voltage provided to the plurality of switches and the input capacitor from an input power supply. 5. The method of claim 4 , wherein the ramp up of the input voltage comprises: gradually switching on the pass switch according to a predetermined time constant provided by a capacitor and resistance element coupled to a gate of the pass switch. 6. The method of claim 1 , further comprising: discharging the flying capacitor via an effective body diode between each drain to source of first to third switches of the plurality of switches coupled in series. 7. A pre-balancing circuit for pre-balancing a switched capacitor converter, comprising: one or more comparator circuits, each configured to monitor charge of a respective capacitor of the switched capacitor converter and generate a pre-balance signal when the charge of the respective capacitor exceeds a threshold charge during a pre-balance phase of the switched capacitor converter; and one or more current sources configured to reduce the charge on capacitors of the switched capacitor converter to a charge level below the threshold charge in response to receiving the pre-balance signal from the one or more comparator circuits. 8. The pre-balancing circuit of claim 7 , wherein the one or more comparator circuits comprise: a first comparator circuit connected to a first current source of the one or more current sources, the first comparator being configured to monitor a first voltage of an output capacitor of the switched capacitor converter, compare the first voltage to a first reference voltage, and to initiate activation of the first current source when the first voltage exceeds the first reference voltage; and a second comparator circuit connected to a second current source of the one or more current sources, the second comparator being configured to monitor a second voltage of an input capacitor of the switched capacitor converter, compare the second voltage to a second reference voltage, and to initiate activation of the second current source when the second voltage exceeds the second reference voltage. 9. The pre-balancing circuit of claim 8 , wherein: the first current source is coupled to the output capacitor, and the second current source is coupled to the input capacitor; the first comparator circuit comprises: a first input configured to receive the first voltage of the output capacitor; a second input configured to receive the first reference voltage; an enable input operative to receive an enable signal to enable the first comparator to monitor charge; and a first current source control output configured to provide to the first current source a first pre-balance signal to initiate activation of the first current source to discharge the output capacitor upon determining that the received first voltage is above a first threshold represented by the first reference voltage; the second comparator circuit comprises: first input configured to receive the second voltage of the input capacitor of the switched capacitor converter; a second input configured to receive the second reference voltage; an enable input operative to receive the enable signal to enable the second comparator to monitor charge; and a second current source control output configured to provide to the second current source a second pre-balance signal to initiate activation of the second current source to discharge the input capacitor upon determining that the received second voltage is above a second threshold represented by the second reference voltage. 10. The circuit of claim 1 , wherein the first and second reference voltages are equal in magnitude. 11. The circuit of claim 1 , wherein the switched capacitor converter is configured as a voltage-multiplier converter. 12. The circuit of claim 1 , further comprising an input supply disconnect switch coupled between a plurality of switches of the switched capacitor converter and an input power supply, the input supply disconnect switch being controlled by the enable signal such that the input supply disconnect switch disconnects the input power supply from the plurality of switches when receiving the enable signal in a second state. 13. The circuit of claim 12 , wherein each of the plurality of switches and the input supply disconnect switch is a transistor having a gate that is coupled to a circuit providing the enable signal. 14. The circuit of claim 13 , wherein at least the input supply disconnect switch is an N-channel metal oxide field effect transistor (NFET). 15. The circuit of claim 13 , further comprising: a third capacitor coupled between the gate of the input supply disconnect switch and a ground; and a resistance element coupled between the gate of the input supply disconnect switch and the circuit providing the enable signal. 16. The circuit of claim 15 , wherein the third capacitor and the resistance element are configured to provide a time constant for turning on the input supply disconnect switch responsive to receiving the enable signal in the second state such that the input supply disconnect switch is turned on at a rate determined by the time constant to provide a ramped voltage from the input power supply to the plurality of switches. 17. The circuit of claim 16 , wherein, upon the output capacitor and the input capacitor being discharged to respective threshold charge levels, the plurality of switches are switched according to a switching scheme and the input supply disconnect switch is turned on at the rate determined by the time constant to provide a soft start of the switched capacitor converter after the pre-balancing of the switched capacitor converter has completed. 18. The circuit of claim 17 , wherein the enable signal is asserted in the second state to create the ramped voltage after the plurality of switches are switched for a period of time. 19. The circuit of claim 1 , wherein the switched capacitor converter comprises: four switches coupled in series between the output capacitor and a ground; and a flying capacitor cou

Assignees

Inventors

Classifications

  • Charge pumps of the Schenkel-type · CPC title

  • H02M3/07Primary

    using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

  • Means for starting or stopping converters · CPC title

  • Electricity · mapped topic

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What does patent US10468978B2 cover?
Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter …
Who is the assignee on this patent?
Linear Tech Corp
What technology area does this patent fall under?
Primary CPC classification H02M3/07. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).