SOI substrate, semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10468486-B2
Application number	US-201815861464-A
Country	US
Kind code	B2
Filing date	Jan 3, 2018
Priority date	Oct 30, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of polycrystalline silicon layers stacked over one another, and a native oxide layer between each adjacent pair of polycrystalline silicon layers.

First claim

What is claimed is:

1. A silicon-on-insulator (SOI) substrate, comprising:
a semiconductor substrate; and
a multi-layered polycrystalline silicon structure over the semiconductor substrate, the multi-layered polycrystalline silicon structure comprising:
a plurality of polycrystalline silicon layers stacked over one another, wherein the plurality of polycrystalline silicon layers comprises N-type or P-type doped polycrystalline silicon layers; and
a native oxide layer between each adjacent pair of the plurality of polycrystalline silicon layers.

2. The SOI substrate of claim 1 , further comprising a buried oxide layer over the multi-layered polycrystalline silicon structure.

3. The SOI substrate of claim 2 , further comprising a superficial silicon layer over the buried oxide layer.

4. The SOT substrate of claim 1 , wherein a number of the polycrystalline silicon layers is ranging from 2 to 6.

5. The SOI substrate of claim 1 , wherein a grain size of each of the polycrystalline silicon layers is smaller than or equal to 0.1 micrometers.

6. The SOI substrate of claim 5 , wherein the grain size of each of the polycrystalline silicon layers is substantially ranging from 0.03 micrometers to 0.1 micrometers.

7. The SOI substrate of claim 1 , wherein a thickness of the multi-layered polycrystalline silicon structure is smaller than or equal to 3 micrometers.

8. The SOI substrate of claim 7 , wherein the thickness of the multi-layered polycrystalline silicon structure is substantially ranging from 0.6 micrometers to 3 micrometers.

9. The SOI substrate of claim 1 , wherein a thickness of the one or more native oxide layer is substantially ranging from 0.5 nanometers to 1.5 nanometers.

10. A semiconductor device, comprising:
a silicon-on-insulator (SOI) substrate, comprising:
a high resistivity handle substrate;
a multi-layered trap-rich structure over the high resistivity handle substrate, the multi-layered trap-rich structure comprising:
a plurality of trap-rich layers stacked over one another, wherein the plurality of trap-rich layers are doped not with carbon; and
a barrier layer between each adjacent pair of the plurality of trap-rich layers;

an insulative layer over the multi-layered trap-rich structure; and

a semiconductor component over the SOI substrate.

11. The semiconductor device of claim 10 , wherein a number of the trap-rich layers is ranging from 2 to 6.

12. The semiconductor device of claim 10 , wherein each of the plurality of trap-rich layers comprise a polycrystalline silicon layer.

13. The semiconductor device of claim 10 , wherein a grain size of each of the trap-rich layers is substantially ranging from 0.03 micrometers to 0.1 micrometers.

14. The semiconductor device of claim 10 , wherein a thickness of the multi-layered trap-rich structure is substantially ranging from 0.6 micrometers to 3 micrometers.

15. The semiconductor device of claim 10 , wherein the one or more barrier layer comprises a native oxide layer.

16. The semiconductor device of claim 10 , wherein a thickness of the one or more barrier layer is substantially ranging from 0.5 nanometers to 1.5 nanometers.

17. A method for manufacturing a silicon-on-insulator (SOI) substrate, comprising:
receiving a semiconductor substrate;
forming a multi-layered polycrystalline silicon structure over the semiconductor substrate, wherein the multi-layered polycrystalline silicon structure comprises:
a plurality of polycrystalline silicon layers stacked over one another, wherein the plurality of polycrystalline silicon layers comprises N-type or P-type doped polycrystalline silicon layers; and
a native oxide layer between each adjacent pair of the plurality of polycrystalline silicon layers; and

forming a buried oxide layer and an active layer over the multi-layered polycrystalline silicon structure.

18. The method of claim 17 , wherein the native oxide layer is formed by disposing the semiconductor substrate in an oxygen-containing environment.

19. The method of claim 17 , wherein a grain size of each of the polycrystalline silicon layers is substantially ranging from 0.03 micrometers to 0.1 micrometers.

20. The method of claim 17 , wherein a grain regrowth of the polycrystalline silicon layers is inhibited by the native oxide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Cheng-Ta
• Tzeng Kuo-Hwa
• Wang Chih-Hao
• Tu Yeur-Luen
• Yu Chung-Yi

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic

• H01L21/7624

  Electricity · mapped topic