Control circuitry for 2D optical metasurfaces

Patent metadata

Field	Value
Publication number	US-10468447-B2
Application number	US-201715824893-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Feb 22, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A 2D hologram system with a matrix addressing scheme is provided. The system may include a 2D array of sub-wavelength hologram elements integrated with a refractive index tunable core material on a wafer substrate. The system may also include a matrix addressing scheme coupled to the 2D array of sub-wavelength hologram elements and configured to independently control each of the sub-wavelength hologram elements by applying a voltage.

First claim

What is claimed is:

1. A 2D hologram system with a matrix addressing scheme, the system comprising:
a 2D array of sub-wavelength hologram elements integrated with a refractive index tunable core material on a wafer substrate; and
a matrix addressing scheme coupled to the 2D array of sub-wavelength hologram elements and configured to independently control each of the sub-wavelength hologram elements by applying a voltage;
wherein the matrix addressing scheme comprises an active matrix addressing scheme for controlling the 2D array of sub-wavelength hologram elements;
wherein each of the hologram elements comprises two dielectric pillars and acts as a capacitor, at least one of the two dielectric pillars being grounded.

2. A 2D hologram system with a matrix addressing scheme, the system comprising:
a 2D array of sub-wavelength hologram elements integrated with a refractive index tunable core material on a wafer substrate; and
a matrix addressing scheme coupled to the 2D array of sub-wavelength hologram elements and configured to independently control each of the sub-wavelength hologram elements by applying a voltage; wherein the matrix addressing scheme comprises a passive matrix addressing scheme for controlling the 2D array of sub-wavelength hologram elements; and
wherein each of the hologram elements comprises a first dielectric pillar and a second dielectric pillar, wherein the tunable core material is positioned between the first and second dielectric pillars, and wherein each hologram element acts as a capacitor.

3. The hologram system of claim 1 , wherein the refractive index tunable core material comprises EP polymer.

4. The hologram system of claim 1 , wherein the wafer substrate comprises a matrix control circuitry having a 2D array of CMOS transistors.

5. The hologram system of claim 4 , wherein the 2D array of CMOS transistors comprise metal-oxide-semiconductor field-effect transistors (MOSFETs).

6. The hologram system of claim 4 , wherein each of the 2D array of CMOS transistors has a Drain connected to each of the hologram elements.

7. The hologram system of claim 6 , wherein all Gates of each row of the 2D array of CMOS transistors are coupled together to a respective ROW line and all Sources of each column of CMOS transistors are coupled together to a respective COLUMN line.

8. The hologram system of claim 7 , wherein each ROW line is configured to digitally control each Gate of the CMOS transistors in the respective row to be “on” and “off”.

9. The hologram system of claim 7 , wherein each COLUMN line is configured to apply an analog voltage through each Source of the CMOS transistors in the column to each of the hologram elements when the Gate of the CMOS transistors is in an “on” state.

10. The hologram system of claim 9 , wherein the analog voltage ranges from −5 v to 5 v.

11. The hologram system of claim 1 , wherein the 2D array of sub-wavelength hologram elements are aligned with each other.

12. The hologram system of claim 2 , wherein the wafer substrate comprises silicon.

13. The hologram system of claim 2 , wherein the refractive index tunable core material comprises liquid crystals or chalcogenide glasses.

14. The hologram system of claim 2 , wherein the first dielectric pillars of each row of the hologram elements are all connected to a ROW line applied with a first analog voltage, and the second dielectric pillars of each column of the hologram elements are all connected to a COLUMN line applied with a second analog voltage.

15. The hologram system of claim 14 , wherein a total analog voltage applied to each of the hologram elements is the sum of the first analog voltage and the second analog voltage.

16. The hologram system of claim 15 , wherein the total analog voltage has a refresh rate of at least 1 k Hz.

17. The hologram system of claim 14 , wherein each of the first analog voltage and the second analog voltage has a refresh rate of at least 1000 times higher than the relaxation rate of the refractive index tunable core material.

18. The hologram system of claim 14 , wherein the refractive index tunable core material in the hologram element has a long term memory such that the hologram element remains stable until a refreshed total analog voltage exceeds a previous value.

19. The hologram system of claim 14 , wherein each of the hologram elements is configured to switch to a different state by refreshing the first analog voltage and/or the second analog voltage.

Assignees

• Elwha Llc

Inventors

• Akselrod Gleb M
• Josberger Erik E
• Weidman Mark C

Classifications

• H10W90/00

  Package configurations · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N23/54

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• G02B5/1809

  with pitch less than or comparable to the wavelength · CPC title

• H01Q15/0066

  said selective devices being reconfigurable, tunable or controllable, e.g. using switches · CPC title