Multilayer ceramic capacitor

US10468189B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10468189-B2
Application numberUS-201514805426-A
CountryUS
Kind codeB2
Filing dateJul 21, 2015
Priority dateAug 1, 2014
Publication dateNov 5, 2019
Grant dateNov 5, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In some embodiments, a multilayer ceramic capacitor 10 has 23 unit capacitors UC 1 to UC 23 , where these 23 unit capacitors UC 1 to UC 23 constitute: a first low-capacitance area LA 1 constituted by three unit capacitors UC 1 to UC 3 ; a high-capacitance area HA constituted by 17 unit capacitors UC 4 to UC 20 whose unit capacitance is greater than that of the three unit capacitors UC 1 to UC 3 ; a second low-capacitance area LA 2 constituted by three unit capacitors UC 21 to UC 23 whose unit capacitance is smaller than that of the 17 unit capacitors UC 4 to UC 20 ; a first variable-capacitance part which is present between the first low-capacitance area LA 1 and high-capacitance area HA, and which includes the two adjacent unit capacitors UC 3 , UC 4 ; and a second variable-capacitance part which is present between the high-capacitance area HA and second low-capacitance area LA 2 , and which includes the two adjacent unit capacitors UC 20 , UC 21.

First claim

Opening claim text (preview).

We claim: 1. A multilayer ceramic capacitor having multiple internal electrode layers stacked with dielectric layers sandwiched in between, with the multiple internal electrode layers connected alternately to a pair of external electrodes, wherein, when a part constituted by two of the internal electrode layers positioned adjacent to each other in a laminating direction and the dielectric layer present between these two internal electrode layers is considered a unit capacitor, then the multilayer ceramic capacitor consists of an n number (n≥x+y+z, where x, y and z are each an integer of 2 or greater) of unit capacitors as a capacitive part; said n number of unit capacitors constituting: (1) a first low-capacitance area constituted by an x number of unit capacitors; (2) a high-capacitance area constituted by a y number of unit capacitors whose unit capacitance is greater than that of the x number of unit capacitors; (3) a second low-capacitance area constituted by a z number of unit capacitors whose unit capacitance is smaller than that of they number of unit capacitors; (4) a first variable-capacitance part which is present between the first low-capacitance area and the high-capacitance area, and which includes two or more adjacent unit capacitors whose unit capacitance difference is larger than a unit capacitance difference of any two adjacent unit capacitors in the first low-capacitance area and the high-capacitance area on a first low-capacitance area side; and (5) a second variable-capacitance part which is present between the high-capacitance area and the second low-capacitance area, and which includes two or more adjacent unit capacitors whose unit capacitance difference between any two adjacent unit capacitors of the two or more adjacent unit capacitors is larger than a unit capacitance difference of any two adjacent unit capacitors in the high-capacitance area and the second low-capacitance area on a second low-capacitance area side, wherein the capacitive part consists of the first low-capacitance area, the high-capacitance area, the second low-capacitance area, the first variable-capacitance part, and the second variable-capacitance part, and wherein all internal electrode layers constituting the capacitive part have a shape of equivalent profile. 2. A multilayer ceramic capacitor according to claim 1 , wherein, when an average unit capacitance of the n number of unit capacitors is given as Cme, a largest unit capacitance difference in the first variable-capacitance part is given as ΔCb 1 , and a largest unit capacitance difference in the second variable-capacitance part is given as ΔCb 2 , then Cme, ΔCb 1 , and ΔCb 2 satisfy conditions of 0.15≤ΔCb 1 /Cme and 0.15≤ΔCb 2 /Cme. 3. A multilayer ceramic capacitor according to claim 1 , wherein, when a largest unit capacitance of the n number of unit capacitors is given as Cmax and a smallest unit capacitance is given as Cmin, then Cmax and Cmin satisfy a condition of 1.4≤Cmax/Cmin. 4. A multilayer ceramic capacitor according to claim 2 , wherein, when a largest unit capacitance of the n number of unit capacitors is given as Cmax and a smallest unit capacitance is given as Cmin, then Cmax and Cmin satisfy a condition of 1.4≤Cmax/Cmin. 5. A multilayer ceramic capacitor according to claim 3 , wherein the condition in claim 3 is 1.4≤Cmax/Cmin≤3.1. 6. A multilayer ceramic capacitor according to claim 4 , wherein the condition in claim 4 is 1.4≤Cmax/Cmin≤3.1. 7. A multilayer ceramic capacitor according to claim 1 , wherein n and a sum (x+z) of x and z satisfy a condition of 0.05≤(x+z)/n. 8. A multilayer ceramic capacitor according to claim 2 , wherein n and a sum (x+z) of x and z satisfy a condition of 0.05≤(x+z)/n. 9. A multilayer ceramic capacitor according to claim 3 , wherein n and a sum (x+z) of x and z satisfy a condition of 0.05≤(x+z)/n. 10. A multilayer ceramic capacitor according to claim 4 , wherein n and a sum (x+z) of x and z satisfy a condition of 0.05≤(x+z)/n. 11. A multilayer ceramic capacitor according to claim 5 , wherein n and a sum (x+z) of x and z satisfy a condition of 0.05≤(x+z)/n. 12. A multilayer ceramic capacitor according to claim 6 , wherein n and a sum (x+z) of x and z satisfy a condition of 0.05≤(x+z)/n. 13. A multilayer ceramic capacitor according to claim 7 , wherein the condition in claim 7 is 0.07≤(x+z)/n≤0.30. 14. A multilayer ceramic capacitor according to claim 1 , wherein all internal electrode layers constituting the capacitive part have an equivalent thickness. 15. A multilayer ceramic capacitor according to claim 1 , wherein all internal electrode layers constituting the capacitive part have a thickness of 1 μm or less. 16. A multilayer ceramic capacitor having multiple internal electrode layers stacked with dielectric layers sandwiched in between, with the multiple internal electrode layers connected alternately to a pair of external electrodes, wherein, when a part constituted by two of the internal electrode layers positioned adjacent to each other in a laminating direction and the dielectric layer present between these two internal electrode layers is considered a unit capacitor, then the multilayer ceramic capacitor has an n number (n≥x+y+z, where x, y and z are each an integer of 2 or greater) of unit capacitors as a capacitive part; said n number of unit capacitors constituting: (1) a first low-capacitance area constituted by an x number of unit capacitors; (2) a high-capacitance area constituted by a y number of unit capacitors whose unit capacitance is greater than that of the x number of unit capacitors; (3) a second low-capacitance area constituted by a z number of unit capacitors whose unit capacitance is smaller than that of they number of unit capacitors; (4) a first variable-capacitance part which is present between the first low-capacitance area and the high-capacitance area, and which includes two or more adjacent unit capacitors whose unit capacitance difference is larger than a unit capacitance difference of any two adjacent unit capacitors in the first low-capacitance area and the high-capacitance area on a first low-capacitance area side; and (5) a second variable-capacitance part which is present between the high-capacitance area and the second low-capacitance area, and which includes two or more adjacent unit capacitors whose unit capacitance difference between any two adjacent unit capacitors of the two or more adjacent unit capacitors is larger than a unit capacitance difference of any two adjacent unit capacitors in the high-capacitance area and the second low-capacitance area on a second low-capacitance area side, wherein the capacitive part consists of the first low-capacitance area, the high-capacitance area, the second low-capacitance area, the first variable-capacitance part, and the second variable-capacitance part, wherein all internal electrode layers constituting the capacitive part have a shape of equivalent profile, and wherein n and a sum (x+z) of x and z satisfy a condition of 0.07≤(x+z)/n≤0.30. 17. A multilayer ceramic capacitor according to claim 16 , wherein, when an average unit capacitance of the n number of unit capacitors is given as Cme, a largest unit capacitance difference in the first variable-capacitance part is given as ΔCb 1 , and a largest unit capacitance difference in the second variable-capacitance part is given as ΔCb 2 , then Cme, ΔCb 1 , and ΔCb 2 satisfy conditions of 0.15≤ΔCb 1 /Cme and 0.15≤ΔCb 2 /Cme. 18. A multilayer ceramic capacitor according to claim 16 , wherein, when a largest unit ca

Assignees

Inventors

Classifications

  • Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

  • Single unit multiple capacitors, e.g. dual capacitor in one coil · CPC title

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

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What does patent US10468189B2 cover?
In some embodiments, a multilayer ceramic capacitor 10 has 23 unit capacitors UC 1 to UC 23 , where these 23 unit capacitors UC 1 to UC 23 constitute: a first low-capacitance area LA 1 constituted by three unit capacitors UC 1 to UC 3 ; a high-capacitance area HA constituted by 17 unit capacitors UC 4 to UC 20 whose unit capacitance is greater than that of the three unit capacitors UC …
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).