DRAM row sparing

Patent metadata

Field	Value
Publication number	US-10468118-B2
Application number	US-201415115971-A
Country	US
Kind code	B2
Filing date	Mar 3, 2014
Priority date	Mar 3, 2014
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

First claim

We claim:

1. A method for dynamic random-access memory (DRAM) row sparing, the method comprising:
during runtime operation of a DRAM device, responsive to identifying a failed row of the DRAM device:
copying first data stored in the failed row to an other storage location such that second data that corresponds to the first data is stored in the other storage location, and temporarily redirecting accesses of the failed row to the other storage location until a fuse in the DRAM device has been blown to replace the failed row with a spare row;
transmitting instructions to blow the fuse to replace the failed row with the spare row;
using, while the fuse is being blown, error-correcting code (ECC) to correct erroneous parts of the second data stored in the other storage location; and
after the fuse is blown, copying the second data from the other storage location to the spare row and redirecting accesses of the failed row to the spare row.

2. The method of claim 1 , wherein:
the DRAM device is a first DRAM device of a plurality of DRAM devices and the other data storage location is part of a second DRAM device of the plurality of DRAM devices;
temporarily redirecting accesses of the failed row to the other storage location comprises temporarily replacing the first DRAM device with the second DRAM device;
the first data is copied from the first DRAM device to the second DRAM device before the first DRAM device is replaced; and
the method further comprising reverting back to using the first DRAM device after the fuse is blown.

3. The method of claim 2 , wherein the reverting back to using the first DRAM device occurs during a system reboot.

4. The method of claim 1 ,
wherein the other storage location is a row buffer in the DRAM device, and
the copying of the second data from the other storage location to the spare row comprises copying, after the fuse is blown, the second data from the row buffer to the spare row.

5. The method of claim 1 ,
wherein the other storage location is a row buffer in a memory controller.

6. The method of claim 1 ,
wherein temporarily redirecting accesses of the failed row to the other storage location includes, while the copying of the first data from the failed row to the other storage location is still ongoing, redirecting to the other storage location accesses of those parts of the failed row that have been copied to the other storage location.

7. The method of claim 6 , comprising:
while the copying of the first data from the failed row to the other storage location is still ongoing, directing to the failed row accesses of those parts of the failed row that have not yet been copied to the other storage location.

8. The method of claim 1 ,
wherein redirecting accesses of the failed row to the spare row includes, while the copying of the second data from the other storage location to the spare row is still ongoing, redirecting to the spare row accesses of those parts of the failed row for which corresponding parts of the second data have been copied from the other storage location to the spare row.

9. The method of claim 8 , comprising:
while the copying of the second data from the other storage location to the spare row is still ongoing, directing to the other storage location accesses of those parts of the failed row for which corresponding parts of the second data have not yet been copied from the other storage location to the spare row.

10. A non-transitory machine-readable storage medium encoded with instructions executable by a processor of a memory controller for dynamic random-access memory (DRAM) row sparing, the machine-readable storage medium comprising:
instructions to, during runtime operation of a DRAM device, copy first data stored in a failed row to an other storage location such that second data that corresponds to the first data is stored in the other storage location, and temporarily redirect accesses of the failed row to the other storage location until a fuse in the DRAM device has been blown to replace the failed row with a spare row;
instructions to blow, during runtime operation of the DRAM device, the fuse to replace the failed row with the spare row;
instructions to use, while the fuse is being blown, error-correcting code (ECC) to correct erroneous parts of the second data stored in the other storage location; and
instructions to, after the fuse is blown, copy the second data from the other storage location to the spare row and redirect accesses of the failed row to the spare row.

11. The machine-readable storage medium of claim 10 ,
wherein the DRAM device is a first DRAM device of a plurality of DRAM devices and the other data storage location is part of a second DRAM device of the plurality of DRAM devices,
the instructions redirect accesses of the failed row to the other storage location include instructions to replace the first DRAM device with the second DRAM device, and
the machine-readable storage medium further comprising instructions to revert back to using the first DRAM device after the fuse is blown.

12. The machine-readable storage medium of claim 10 ,
wherein the other storage location is a row buffer in the DRAM device.

13. The machine-readable storage medium of claim 10 ,
wherein the other storage location is a row buffer in a memory controller.

14. The non-transitory machine-readable of claim 10 ,
wherein temporarily redirecting accesses of the failed row to the other storage location includes, while the copying of the first data from the failed row to the other storage location is still ongoing, redirecting to the other storage location accesses of those parts of the failed row that have been copied to the other storage location.

15. The non-transitory machine-readable of claim 14 , comprising instructions to:
while the copying of the first data from the failed row to the other storage location is still ongoing, direct to the failed row accesses of those parts of the failed row that have not yet been copied to the other storage location.

16. The non-transitory machine-readable of claim 10 ,
wherein redirecting accesses of the failed row to the spare row includes, while the copying of the second data from the other storage location to the spare row is still ongoing:
redirecting to the spare row accesses of those parts of the failed row for which corresponding parts of the second data have been copied from the other storage location to the spare row; and
directing to the other storage location accesses of those parts of the failed row for which corresponding parts of the second data have not yet been copied from the other storage location to the spare row.

17. A non-transitory machine-readable storage medium encoded with instructions executable by a processor for dynamic random-access memory (DRAM) row sparing, the machine-readable storage medium comprising:
instructions to identify a DRAM device having a failed row;
instructions to identify a row number of the failed row of the DRAM device;
instructions to, responsive to identifying the failed row, during runtime operation of the DRAM device:
copy first data stored in the failed row to an other storage location such that second data that corresponds to the first data is stored in the other storage location;
temporarily redirect accesses of the failed row to the other storage location until a fuse in the DRAM device has been blown to replace the failed row with a spare row;
blow the fuse to replace the failed row with the spare row;
while the fuse is being blown, use error-correcting code (ECC) to correc

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Walton Andrew C
• Benedict Melvin K
• Pope Eric L
• Handgen Erin A

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/065

  Replication mechanisms · CPC title