Methods of operating a memory device

Patent metadata

Field	Value
Publication number	US-10468116-B2
Application number	US-201715689459-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Nov 8, 2011
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Methods of operating a memory device include comparing an input address to one or more addresses stored in the memory device and indicative of problematic memory cells of the memory device, determining a status value of an indicator corresponding to a matched address if the input address matches a stored address, and storing data corresponding to the input address to a first memory array of the memory device and to a second memory array of the memory device if the indicator has a first status value. Methods may further include storing the data corresponding to the input address to only the first memory array or the second memory array if the indicator has a second status value.

First claim

What is claimed is:

1. A method of operating a memory device, the method performed by the memory device comprising:
comparing an input address to one or more addresses stored in the memory device, wherein each stored address of the one or more addresses stored in the memory device are indicative of problematic memory cells of the memory device;
if the input address matches a stored address of the one or more addresses stored in the memory device, determining a status value of an indicator corresponding to the matched address;
if the indicator has a first status value indicative of a problematic memory cell in a memory cache of the memory device, storing data corresponding to the input address to a first memory array of the memory device, and storing the data corresponding to the input address to a second memory array of the memory device; and
if the indicator has a second status value different than the first status value, storing the data corresponding to the input address to only the first memory array or the second memory array;
wherein the memory cache is configured for communication with the first memory array and is configured for communication with the second memory array.

2. The method of claim 1 , further comprising:
programming known patterns of data to memory cells of the first memory array, to memory cells of the second memory array, and to memory cells of the memory cache of the memory device;
reading the memory cells of the first memory array, the second memory array and the memory cache;
if the data read from a memory cell of the memory cache is different than the data known to be programmed into that memory cell, storing an address corresponding to that memory cell in a third memory array of the memory device and in a fourth memory array of the memory device, and storing an indicator corresponding to that address and having the first status value in the third memory array and in the fourth memory array; and
if the data read from a memory cell of the first memory array is different than the data known to be programmed into that memory cell, storing an address corresponding to that memory cell in the third memory array, and storing an indicator corresponding to that address and having a second status value in the third memory array; and
if the data read from a memory cell of the second memory array is different than the data known to be programmed into that memory cell, storing an address corresponding to that memory cell in the fourth memory array, and storing an indicator corresponding to that address and having the second status value in the fourth memory array.

3. The method of claim 2 , wherein storing an address in the third memory array comprises storing that address in a first content-addressable memory array of the memory device, and wherein storing an address in the fourth memory array comprises storing that address in a second content-addressable memory array of the memory device.

4. The method of claim 1 , further comprising storing each address of the one or more addresses to one or both of a third memory array of the memory device and a fourth memory array of the memory device prior to comparing the input address.

5. The method of claim 4 , wherein storing each address of the one or more addresses to one or both of the third memory array and the fourth memory comprises storing each address of the one or more addresses from a read-only memory of the memory device.

6. The method of claim 4 , wherein storing each address of the one or more addresses to one or both of the third memory array and the fourth memory comprises storing a particular address to the third memory array and storing the particular address to the fourth memory array if an indicator corresponding to the particular address has the first status value.

7. The method of claim 6 , further comprising storing the particular address to only the third memory array or the fourth memory array if the indicator corresponding to the particular address has a second status value.

8. The method of claim 1 , wherein storing the data corresponding to the input address to the first memory array and to the second memory array comprises storing the data corresponding to the input address to redundant memory cells of the first memory array, and storing the data corresponding to the input address to redundant memory cells of the second memory array.

9. A method of operating a memory device, the method performed by the memory device comprising:
comparing an input address to one or more addresses stored in the memory device, wherein each address of the one or more addresses comprises a corresponding indicator having a status value, and wherein each address of the one or more addresses is stored in at least one memory array selected from a group consisting of a first memory array of the memory device and a second memory array of the memory device;
if the input address matches a stored address of the one or more addresses, determining a status value of an indicator corresponding to the matched address;
if the indicator has a first status value indicative of a problematic memory cell in a memory cache of the memory device, storing data corresponding to the input address to a third memory array of the memory device and to a fourth memory array of the memory device;
if the indicator has a second status value different than the first status value, and the stored address is stored in the first memory array, storing the data corresponding to the input address to the third memory array without storing the data corresponding to the input address to the fourth memory array; and
if the indicator has the second status value, and the stored address is stored in the second memory array, storing the data corresponding to the input address to the fourth memory array without storing the data corresponding to the input address to the third memory array.

10. The method of claim 9 , wherein, when the indicator has the first status value, the input address corresponds to an address of a memory cache of the memory device comprising the first memory array and the second memory array, and in communication with the third memory array and the fourth memory array.

11. The method of claim 10 , wherein, when the indicator has the second status value, the input address corresponds to an address of the third memory array or to an address of the fourth memory array.

12. The method of claim 9 , wherein, for each address of the one or more addresses stored in the memory device, the method further comprises:
storing that address to the first memory array and to the second memory array prior to comparing the input address if its corresponding indicator has the first status value;
storing that address to the first memory array prior to comparing the input address if its corresponding indicator has the second status value and that address corresponds to a memory cell of the third memory array; and
storing that address to the second memory array prior to comparing the input address if its corresponding indicator has the second status value and that address corresponds to a memory cell of the fourth memory array.

13. The method of claim 9 , wherein storing the data corresponding to the input address to the third memory array comprises storing the data corresponding to the input address to at least one redundant memory cell of the third memory array; and wherein storing the data corresponding to the input address to the fourth memory array comprises storing the data corresponding to the input address to at least one redundant memory cell of the fourth memory array.

14. The method of claim 13 , wherein

Assignees

• Micron Technology Inc

Inventors

• Ha Chang Wan

Classifications

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G11C29/08

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G11C15/00

  Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title