High speed processing of financial information using FPGA devices

Patent metadata

Field	Value
Publication number	US-10467692-B2
Application number	US-201314049591-A
Country	US
Kind code	B2
Filing date	Oct 9, 2013
Priority date	Jun 19, 2006
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to generate a plurality of financial market data messages from a plurality of the data fields, each generated message having a specified message format.

First claim

What is claimed is:

1. An apparatus for processing financial market data, the apparatus comprising:
a ticker plant configured to receive a financial market data feed from an exchange, wherein the financial market data comprises a plurality of streaming messages within the feed that represent a plurality of offers to buy and sell a plurality of financial instruments, the messages comprising a plurality of data values corresponding to a plurality of data fields, the ticker plant comprising a reconfigurable logic device, a processor in cooperation with the reconfigurable logic device, and a memory;
wherein the processor is configured to normalize the financial market data and deliver the normalized financial market data to the reconfigurable logic device;
wherein the memory is configured to store a data dictionary, the data dictionary comprising a plurality of entries corresponding to a message format, the entries configured to describe (1) a plurality of message fields for the message format, (2) a plurality of positions for the message fields with respect to the message format, (3) a plurality of sizes for the message fields with respect to the message format, and (4) metadata for the message fields with respect to the message format; and
wherein the reconfigurable logic device comprises firmware logic, the firmware logic configured to (1) access the memory to read the data dictionary entries, and (2) process the normalized financial market data and arrange the data values from the normalized financial market data into a plurality of the message fields in accordance with the read data dictionary entries to thereby generate from the processed normalized financial market data a plurality of financial market data messages having the message format, the generated financial market data messages comprising (i) a plurality of the arranged data values in the message fields, wherein the message fields are positioned and sized within the generated financial market data messages in accordance with the positions and sizes from the read data dictionary entries, and (ii) metadata from the read data dictionary entries corresponding to the message fields of the generated financial market data messages; and
wherein the reconfigurable logic device and the memory are configured to support generation of financial market data messages of different message formats by changing the data dictionary entries to be accessed and read by the firmware logic and without altering the firmware logic.

2. The apparatus of claim 1 wherein the metadata in the data dictionary entries comprise a field identifier and a data type.

3. The apparatus of claim 1 wherein the memory is external to the reconfigurable logic device.

4. The apparatus of claim 1 wherein the reconfigurable logic device comprises a plurality of firmware application modules (FAMs) arranged as a processing pipeline, the FAMs including a message formatter FAM and at least one FAM that is upstream from the message formatter FAM;
wherein the at least one upstream FAM is configured to receive streaming normalized financial market data and perform a data processing operation on at least a portion of the streaming normalized financial market data;
wherein the message formatter FAM is configured to (1) receive normalized financial market data that was previously processed by the at least one upstream FAM, and (2) perform the access, process, and arrange operations with respect to the received normalized financial market data to thereby generate the financial market data messages having the message format;
wherein the at least one upstream FAM is configured to operate simultaneously with the message formatter FAM in a pipelined fashion such that the message formatter FAM is configured to operate on normalized financial market data that was previously processed by the at least one upstream FAM while the at least one upstream FAM operates on different normalized financial market data.

5. The apparatus of claim 4 wherein the at least one upstream FAM comprises at least one member of the group consisting of (1) a symbol ID mapping FAM, (2) a value cache update FAM, (3) a top 10 lists generator FAM, (4) a minute bar generator FAM, (5) an interest entitlement filter FAM, and (6) a programmatic calculation engine FAM.

6. The apparatus of claim 4 wherein the processing pipeline further comprises (1) a message parsing FAM upstream from the at least one upstream FAM, and (2) a message synchronization buffer downstream from the message parsing FAM;
wherein the message parsing FAM is configured to (1) receive a normalized financial market data message, (2) parse the received normalized financial market data message into a plurality of fields of financial market data, and (3) provide at least a plurality of the parsed financial market data fields to the message synchronization buffer for buffering therein;
wherein the at least one upstream FAM is further configured to perform the data processing operation on a select subset of the parsed financial market data; and
wherein the message formatter FAM is configured to generate a plurality of the financial market data messages having the message format based on the buffered data fields in the message synchronization buffer and the processed financial market data produced by the at least one upstream FAM.

7. The apparatus of claim 4 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA), the processing pipeline being resident on the FPGA, the processing pipeline configured to operate at hardware processing speeds.

8. The apparatus of claim 1 wherein the message format comprises a fixed record format.

9. The apparatus of claim 1 wherein the message format comprises a FIX message format.

10. The apparatus of claim 1 wherein the message format comprises a FAST message format.

11. The apparatus of claim 1 wherein the data dictionary further comprises a plurality of entries corresponding to a plurality of different message formats, and wherein the reconfigurable logic device is further configured to access the data dictionary to determine a message format for each financial market data message that is to be generated.

12. The apparatus of claim 11 wherein the reconfigurable logic device comprises a plurality of firmware application modules (FAMs) arranged as a message transformation pipeline, the message transformation pipeline comprising a message parsing FAM and a message formatter FAM that is downstream from the message formatting FAM;
wherein the message parsing FAM is configured to (1) receive a plurality of streaming normalized financial market data messages having a first message format, (2) access the memory to read a plurality of data dictionary entries corresponding to the first message format, and (3) parse the received normalized financial market data messages into constituent fields of financial market data in accordance with the read data dictionary entries corresponding to the first message format; and
wherein the message formatter FAM is configured to (1) receive a plurality of parsed financial market data fields, and (2) perform the access, process, and arrange operations with respect to the received parsed financial market data fields and a second message format from the data dictionary to generate a plurality of financial market data messages having the second message format; and
wherein the reconfigurable logic device and the memory are configured to support processing of different message formats by changing the data dictionary entries to be accessed and read by the message parsing FAM and the message formatter FAM and without altering the message parsing FAM or the me

Assignees

• Ip Reservoir Llc

Inventors

• Parsons Scott
• Taylor David E
• Schuehler David Vincent
• Franklin Mark A
• Chamberlain Roger D

Classifications

• G06Q40/06

  Asset management; Financial planning or analysis · CPC title

• G06Q40/00

  Finance; Insurance; Tax strategies; Processing of corporate or income taxes · CPC title

• G06Q40/04 Primary

  Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange · CPC title