Implementing cable failover in multiple cable PCI Express IO interconnections

Patent metadata

Field	Value
Publication number	US-10467110-B2
Application number	US-201715817226-A
Country	US
Kind code	B2
Filing date	Nov 19, 2017
Priority date	Oct 27, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

First claim

What is claimed is:

1. A computer system for implementing cable failover in a PCIE link including multiple cable Peripheral Component Interconnect Express (PCI-Express or PCIE) IO interconnections attached to an IO drawer, comprising:
a processor;
system firmware provided with said processor;
a PCIE host bridge (PHB); said PHB connected to said processor;
the PCIE link including multiple cable PCIE IO interconnections coupled between said PCIE host bridge (PHB) and an PCIE enclosure with a respective Inter-Integrated Circuit (I2C) bus conveying IO control signaling;
PCIE multiplexer logic coupled between said PHB and the multiple cable PCIE IO interconnections coupled to the PCIE enclosure;
said processor using said system firmware for periodically implementing health check functions and responsive to a hardware interrupt to determine if the PCIE link is degraded;
said processor using said system firmware responsive to detecting a degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying a functional high byte cable, and identifying a faulted low byte cable, performing a full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure; and
said processor using said system firmware, running the PCIE link in a degraded state with half a normal configuration until the PCIE cable is serviced to restore full width.

2. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware implementing health check functions for the PCIE IO interconnections to identify the degraded link.

3. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware for implementing health check functions for the PCIE IO interconnections to identify a functional high byte cable.

4. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware for interrogating components to determine if a functional high byte cable exists.

5. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware implementing health check functions for the PCIE IO interconnections to identify the faulted low byte cable.

6. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware for interrogating components to determine if a faulted low byte cable exists.

7. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware, disabling the low byte cable.

8. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware, reconfiguring the PHB to reverse the PCIE lane order.

9. The system as recited in claim 1 , wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware, detecting link transmission activity.

Assignees

• IBM

Inventors

• Arroyo Jesse P
• Engel Christopher J
• Naderi Kaveh
• Smith James E

Classifications

• G06F11/2017

  where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/1616 Primary

  where the redundant component is an I/O device or an adapter therefor · CPC title

• G06F13/4068

  Electrical coupling · CPC title