Method and apparatus for nearest potential store tagging

Patent metadata

Field	Value
Publication number	US-10467010-B2
Application number	US-201414209736-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Mar 15, 2013
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.

First claim

What is claimed is:

1. A method for performing memory disambiguation in an out-of-order microprocessor pipeline, said method comprising:
storing a tag with a load operation, wherein said tag is an identification number representing a store instruction nearest to said load operation, wherein said store instruction is older with respect to said load operation and wherein said store has potential to result in a read-after-write (RAW) violation in conjunction with said load operation if said store instruction targets a same memory address as said load operation;
issuing said load operation from an instruction scheduling module;
acquiring data for said load operation speculatively after said load operation has arrived at a load store queue module;
determining if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag, wherein said identification number of said last contiguous issued store indicates a position in an instruction stream to which all store instructions have been resolved and is associated with a global signal tracked by a reorder buffer (ROB), wherein the last contiguous issued store was issued for execution prior to determining if the identification number associated with the last contiguous issued store is equal to or greater than said tag;
in response to a determination that said identification number associated with said last contiguous issued store is equal to or greater than said tag, validating said data acquired by said load operation by performing an address check against stores in said load store queue module to determine if any of said stores has potential to result in a RAW hazard, wherein said stores are older than said load operation; and
broadcasting, in the out-of-order microprocessor pipeline, said identification number associated with said last contiguous issued store during every cycle of said out-of-order microprocessor pipeline.

2. The method of claim 1 , further comprising:
committing said load operation in response to a determination that none of said stores has potential to result in the RAW hazard.

3. The method of claim 1 , wherein said determining is performed in response to said instruction scheduling module broadcasting said identification number associated with said last contiguous issued store.

4. The method of claim 1 , wherein said identification number associated with said tag is assigned by said reorder buffer (ROB).

5. The method of claim 1 , wherein said storing is performed using an inheritance process, wherein said identification number associated with said tag is inherited from an instruction prior to said load operation.

6. The method of claim 1 , wherein an address of the last contiguous issued store was disambiguated or resolved prior to determining if the identification number associated with the last contiguous issued store is less than said tag.

7. A processor unit configured to perform a method for performing memory disambiguation in an out-of-order microprocessor pipeline, said method comprising:
storing a tag with a load operation, wherein said tag is an identification number representing a store instruction nearest to said load operation, wherein said store instruction is older with respect to said load operation and wherein said store has potential to result in a read-after-write (RAW) violation in conjunction with said load operation if said store instruction targets a same memory address as said load operation;
issuing said load operation from an instruction scheduling module;
acquiring data for said load operation speculatively after said load operation has arrived at a load store queue module;
determining if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag, wherein said identification number of said last contiguous issued store indicates a position in an instruction stream to which all store instructions have been resolved and is associated with a global signal tracked by a reorder buffer (ROB), wherein the last contiguous issued store was issued for execution prior to determining if the identification number associated with the last contiguous issued store is equal to or greater than said tag;
in response to a determination that said identification number associated with said last contiguous issued store is equal to or greater than said tag, validating said data acquired by said load operation by performing an address check against stores in said load store queue module to determine if any of said stores has potential to result in a RAW hazard, wherein said stores are older than said load operation; and
broadcasting, in the processor unit, said identification number associated with said last contiguous issued store during every cycle of said out-of-order microprocessor pipeline.

8. The processor unit as described in claim 7 , wherein said method further comprises:
committing said load operation in response to a determination that none of said stores has potential to result in the RAW hazard.

9. The processor unit as described in claim 7 , wherein said determining is performed in response to said instruction scheduling module broadcasting said identification number associated with said last contiguous issued store.

10. The processor unit as described in claim 7 , wherein said identification number associated with said tag is assigned by the reorder buffer (ROB).

11. The processor unit as described in claim 7 , wherein said storing is performed using an inheritance process, wherein said identification number associated with said tag is inherited from an instruction prior to said load operation.

12. An apparatus configured to perform a method for performing memory disambiguation in an out-of-order microprocessor pipeline, said apparatus comprising:
a memory;
a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and further wherein said processor is configured to:
store a tag with a load operation, wherein said tag is an identification number representing a store instruction nearest to said load operation in program order, wherein said store instruction is older with respect to said load operation and wherein said store has potential to result in a read-after-write (RAW) violation in conjunction with said load operation if said store instruction targets a same memory address as said load operation;
issue said load operation from an instruction scheduling module;
acquire data for said load operation speculatively after said load operation has arrived at a load store queue module;
determine if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag, wherein said identification number of said last contiguous issued store indicates a position in an instruction stream to which all store instructions have been resolved and is associated with a global signal tracked by a reorder buffer (ROB), wherein the last contiguous issued store was executed prior to determining if the identification number associated with the last contiguous issued store is equal to or greater than said tag; and
gate a validation process for said load operation in response to a determination of whether said identification number associated with said last contiguous issued store is equal to or greater than said tag, wherein the validation process comprises validating said data acquired by said load operation by performing an address check against stores in said load store queue module to determine if any

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad A
• Singh Mandeep

Classifications

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/3855

  Physics · mapped topic