Memory system

Patent metadata

Field	Value
Publication number	US-10466909-B2
Application number	US-201615294320-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 16, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices respectively working as cache memories for the second memory device and the data storage memory,
wherein the first and second memories are separated from the processor,
wherein the first and second memory devices and the processor are directly connected to one another through a common bus,
wherein the processor separately communicates with each of the first and second memories, and
wherein the first and second memory controllers transfer a signal and directly exchange data between the first and second memory devices based on at least one of values of a memory selection field and a handshaking information field included in the signal under control of the processor.

2. The memory system of claim 1 ,
wherein the first and second memory have first and second latencies, respectively,
wherein the first and second memory devices maintain information of the first and second latencies, respectively, and
wherein the processor separately accesses each of the first and second memories according to the information of the first and second latencies provided from the first and second memory devices.

3. The memory system of claim 1 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

4. The memory system of claim 1 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the first memory device to the second memory device, a data ready signal from the second memory device to the first memory device and a session start signal from the first memory device to the second memory device.

5. The memory system of claim 1 , wherein the first memory device is a volatile memory device.

6. The memory system of claim 1 , wherein the second memory device is a non-volatile random access memory device.

7. The memory system of claim 6 , wherein the non-volatile memory device is a non-volatile random access memory device.

8. A memory system comprising:
a common bus;
a first memory device directly connected to the common bus, and including a first memory and a first memory controller suitable for controlling the first memory to store data;
a second memory device directly connected to the common bus, and including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor directly connected to the common bus, and executing an operating system (OS) and an application separately accessing a data storage memory through each of the first and second memory devices respectively working as cache memories for the second memory device and the data storage memory,
wherein the first and second memories are separated from the processor, and
wherein the first and second memory controllers transfer a signal and directly exchange data between the first and second memory devices based on at least one of values of a memory selection field and a handshaking information field included in the signal under control of the processor.

9. The memory system of claim 8 ,
wherein the first and second memory have first and second latencies, respectively,
wherein the first and second memory devices maintain the information of the first and second latencies, respectively, and
wherein the processor separately accesses each of the first and second memories according to the information of the first and second latencies provided from the first and second memory devices.

10. The memory system of claim 8 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

11. The memory system of claim 8 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the first memory device to the second memory device, a data ready signal from the second memory device to the first memory device and a session start signal from the first memory device to the second memory device.

12. The memory system of claim 8 , wherein the first memory device is a volatile memory device.

13. The memory system of claim 8 , wherein the second memory device is a non-volatile random access memory device.

14. The memory system of claim 13 , wherein the non-volatile memory device is a non-volatile random access memory device.

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang-Hyun
• Kim Min-Chang
• Lee Do-Yun
• Lee Yong-Woo
• Lee Jae-Jin
• Jung Hun-Sam

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F13/4286

  using a handshaking protocol, e.g. RS232C link · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title